Signal & Power Integrity Tech Lead – Remote/Hybrid

Cisco Systems

Roseville (CA)

Hybrid

USD 214,000 - 356,000

Full time

5 days ago
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Job summary

Cisco Silicon One in San Jose, CA is seeking a highly qualified Signal and Power Integrity Technical Leader to guide our packaging team in defining, designing, and verifying high‑volume ASIC packages. You will develop design rules for ultra‑high‑speed signaling, analyze SI/PI across interposer, substrate and PCB, and mentor engineers while driving continuous improvement in multi‑discipline teams.

Strong background in 56G PAM4, SerDes, and 2.5D packaging, plus hands‑on tools experience (Keysight

Qualifications

  • Bachelor’s degree in Electrical Engineering; 10+ years of SI/PI experience or
  • Master’s degree in Electrical Engineering; 8+ years of SI/PI experience or
  • PhD in Electrical Engineering; 5+ years of SI/PI experience.

Responsibilities

  • Define rules for ultra-high-speed signaling to meet power, performance, and area goals.
  • Analyze substrate SI and PI; collaborate with layout to optimize interposer, substrate, and PCB.
  • Design, document, and develop ASIC packages for high-volume, high-quality releases.
  • Lead or participate in chip architecture discussions for high-performance ASICs.
  • Mentor SI team and influence packaging/hardware teams; drive design reviews and postmortems.

Skills

Signal Integrity
Power Integrity
Team Leadership
High-Speed Signaling
PAM4/SerDes
Engineering Collaboration

Education

Bachelor's degree in Electrical Engineering
Master's degree in Electrical Engineering
PhD in Electrical Engineering

Tools

Keysight ADS
Ansys HFSS/EM flow
Cadence APD
MATLAB
Python scripting
Raptor-X

Job description

Cisco Silicon One in San Jose, CA is seeking a highly qualified Signal and Power Integrity Technical Leader to guide our packaging team in defining, designing, and verifying high‑volume ASIC packages. You will develop design rules for ultra‑high‑speed signaling, analyze SI/PI across interposer, substrate and PCB, and mentor engineers while driving continuous improvement in multi‑discipline teams.

Strong background in 56G PAM4, SerDes, and 2.5D packaging, plus hands‑on tools experience (Keysight

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