Signal & Power Integrity Tech Lead — Remote/Hybrid

Cisco Systems; Boston (MA); Remote; USD 214,000 - 356,000; Full time

Job summary

Cisco Silicon One is seeking a Signal and Power Integrity Technical Leader to drive the next generation of ASIC packaging. You will lead the Silicon Packaging SI/PI team to define, design, and verify packaging for Cisco platforms, ensuring power, performance, and area goals are met.

The role requires deep expertise in high-speed signaling, SI/PI analysis, and collaboration with layout and system teams across complex ASIC packaging.

Qualifications

• Bachelor’s degree in Electrical Engineering with 10+ years of SI/PI experience, or advanced degrees with fewer years.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Experience with 56G PAM4 and above, high-speed SerDes, channel modeling, BER prediction, transmission line theory, and electromagnetics.
• Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
• Experience with SPICE.

Responsibilities

• Lead the Silicon Packaging SI/PI team to define, design, and verify ASIC packaging for Cisco platforms.
• Develop, document, and implement design rules for ultra-high-speed signaling to meet power/performance/area goals.
• Analyze substrate SI/PI and collaborate with layout to optimize interposer, substrate, and PCB.
• Design and develop ASIC packages for high-volume, high-quality releases with post-layout extraction and reporting.
• Mentor the SI team and influence packaging/hardware teams to meet technical specs.

Skills

Signal integrity

Power integrity

High-speed signaling

ASIC packaging

2.5D packaging

MATLAB/Python scripting

Team leadership

Debugging

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Keysight ADS

Ansys HFSS

Cadence APD

Cadence SPICE

Job description

Cisco Silicon One is seeking a Signal and Power Integrity Technical Leader to drive the next generation of ASIC packaging. You will lead the Silicon Packaging SI/PI team to define, design, and verify packaging for Cisco platforms, ensuring power, performance, and area goals are met.

The role requires deep expertise in high-speed signaling, SI/PI analysis, and collaboration with layout and system teams across complex ASIC packaging.