ASIC Packaging SI/PI Engineer - High-Speed 56G SerDes

Cisco Systems, Inc; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Cisco Systems, Inc. in San Jose, CA is seeking a Signal and Power Integrity Engineer to join the Cisco Silicon One team. You will design, verify, and optimize packaging for high-performance ASICs and collaborate closely with the layout and design teams, with a commute to the office required 4–5 days per week.

Candidates should have a degree in electrical engineering with 4+ years for Bachelor's or 2+ years for Master’s and hands-on SI/PI, high-speed design, and industry tools.

Qualifications

• Bachelor's in Electrical Engineering with 4+ years SI/PI experience.
• Master's in Electrical Engineering with 2+ years SI/PI experience.
• PhD in Electrical Engineering with 0+ years experience; equivalent work.

Responsibilities

• Develop, document, and verify ASIC packaging for Cisco platforms.
• Analyze substrate SI/PI and provide feedback to layout teams.
• Create post-layout extraction and reporting for high-volume release.
• Collaborate with system partners, vendors, and design leads to resolve complex issues.
• Define design rules for ultra-high-speed signaling to meet power, performance, and area goals.

Skills

High-Speed Design

SI/PI Simulation

Transmission Line Theory

PAM4 SerDes

BER Prediction

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Job description

Cisco Systems, Inc. in San Jose, CA is seeking a Signal and Power Integrity Engineer to join the Cisco Silicon One team. You will design, verify, and optimize packaging for high-performance ASICs and collaborate closely with the layout and design teams, with a commute to the office required 4–5 days per week.

Candidates should have a degree in electrical engineering with 4+ years for Bachelor's or 2+ years for Master’s and hands-on SI/PI, high-speed design, and industry tools.