ASIC Packaging Signal/Power Integrity Hardware Engineer (Hybrid)

Cisco Systems, Inc; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Cisco Systems, Inc. in San Jose, CA is seeking a Signal and Power Integrity Engineer to join the Cisco Silicon One team. You will design, verify, and optimize packaging for high-performance ASICs and collaborate closely with the layout and design teams, with a commute to the office required 4–5 days per week.

Candidates should have a degree in electrical engineering with 4+ years for Bachelor's or 2+ years for Master’s and hands-on SI/PI, high-speed design, and industry tools.

Qualifications

• Bachelor's in Electrical Engineering with 4+ years SI/PI experience.
• Master's in Electrical Engineering with 2+ years SI/PI experience.
• PhD in Electrical Engineering with 0+ years experience; equivalent work.

Responsibilities

• Develop, document, and verify ASIC packaging for Cisco platforms.
• Analyze substrate SI/PI and provide feedback to layout teams.
• Create post-layout extraction and reporting for high-volume release.
• Collaborate with system partners, vendors, and design leads to resolve complex issues.
• Define design rules for ultra-high-speed signaling to meet power, performance, and area goals.

Skills

High-Speed Design

SI/PI Simulation

Transmission Line Theory

PAM4 SerDes

BER Prediction

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Job description

This position requires that you live within commuting distance of our San Jose, CA office and commute to the office at least 4-5 days per week.

Meet the Team

Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry!

Your Impact

• We are seeking a qualified Signal and Power Integrity Engineer to help us develop our next generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.
• Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
• Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 2+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 0+ years of related experience, or equivalent related work experience.
• High-Speed Design & Theory: Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
• SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.