Signal & Power Integrity Lead — Remote ASIC Packaging

Cisco Systems; San Diego (CA); Hybrid; USD 214,000 - 310,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) with Cisco matching

Paid parental leave

Disability coverage

Job summary

Cisco Systems is seeking a senior Signal and Power Integrity Technical Leader in the San Jose area to guide our next generation ASIC packaging efforts. Lead the SI/PI team, define rules for ultra‑high‑speed signaling, and work with layout to optimize interposer, substrate, and PCB solutions.

You will mentor engineers, drive post-layout extraction, and shape architecture discussions for high‑performance ASICs, including 5nm/3nm nodes and advanced packaging technologies.

Qualifications

• Minimum 10+ years in signal and/or power integrity (or 8+ with Master's, 5+ with PhD).
• Experience with multiple high‑speed ASIC tape‑outs from a package perspective.
• Expertise in 56G PAM4, high‑speed SerDes, channel modeling, BER, transmission line theory, and EM.
• Hands‑on lab experience with industry tools (ADS, HFSS, Cadence).
• Experience with SPICE and IC/packaging design flows.

Responsibilities

• Define and lead ASIC packaging SI/PI efforts across interposer, substrate, and PCB.
• Develop design rules for ultra‑high-speed signaling meeting power, performance, and area goals.
• Lead analysis of substrate SI/PI and collaborate with layout teams to optimize interposer packaging.
• Design and develop ASIC packages for high‑volume, high-quality release with post-layout extraction.

Skills

High‑speed signaling

PAM4 / SerDes

Lab tools expertise

SPICE simulations

Mentoring

Education

Bachelor's degree in Electrical Engineering

Master's/PhD in Electrical Engineering

Tools

Keysight ADS

Ansys HFSS/EM

Cadence APD

Matlab / Python scripting

Job description

Cisco Systems is seeking a senior Signal and Power Integrity Technical Leader in the San Jose area to guide our next generation ASIC packaging efforts. Lead the SI/PI team, define rules for ultra‑high‑speed signaling, and work with layout to optimize interposer, substrate, and PCB solutions.

You will mentor engineers, drive post-layout extraction, and shape architecture discussions for high‑performance ASICs, including 5nm/3nm nodes and advanced packaging technologies.