Signal Integrity Engineering Manager - PAM4 SerDes Lead

Hewlett Packard Enterprise Development LP; Sunnyvale (CA); Hybrid; USD 183,000 - 390,000; Full time

Job summary

Hewlett Packard Enterprise Development LP seeks a Networking Signal Integrity Engineering Manager to lead a team focused on PAM4 SerDes and SI rule development for hardware networking systems. The role requires technical proficiency in PAM4 SerDes/SI and collaboration across HW, SW, PCB layout, and Manufacturing Test in an onsite office in California.

You will manage a team of SI engineers, coordinate with global SI leadership, and ensure on-time, high-quality SI deliverables for new products

Qualifications

• Must have 5+ years managing signal integrity engineers.
• Must have knowledge of PAM4 SerDes and Signal Integrity, Clocking, Phase lock Loops.
• Must have knowledge of SI CAD tools, HFSS, SiWave, Keysight ADS.
• Must have knowledge of SI lab equipment, DCAX sampling scope, UXR real time scope, VNA, TDR, Signal Source Analyzer for phase noise measurements.

Responsibilities

• Lead team of Signal Integrity engineers working on multiple new programs to implement PAM4 serdes and develop signal integrity rules for HW network systems.
• Work constructively with other functions HW, SW, PCB layout and other functions to develop new products.
• Respond and resolve Field Escalations and emergency customer escalations.
• Work with SI management across geography US/India.
• Deliver on time with high quality SI deliverables for new products.

Skills

PAM4 SerDes

Signal Integrity

Clocking

Phase-Locked Loops

SI CAD tools

HFSS

SiWave

Keysight ADS

SI lab equipment

VNA

TDR

Signal Source Analyzer

5+ years managing

Education

B.S. Electrical Engineering

M.S. Electrical Engineering preferred

Tools

Ansys HFSS

Cadence Allegro

Cadence Allegro Constraint Manager

Job description

Hewlett Packard Enterprise Development LP seeks a Networking Signal Integrity Engineering Manager to lead a team focused on PAM4 SerDes and SI rule development for hardware networking systems. The role requires technical proficiency in PAM4 SerDes/SI and collaboration across HW, SW, PCB layout, and Manufacturing Test in an onsite office in California.

You will manage a team of SI engineers, coordinate with global SI leadership, and ensure on-time, high-quality SI deliverables for new products