Senior SerDes Systems Engineer - High-Speed Transceivers

Synopsys Inc; Boxborough (MA); On-site; USD 140,000 - 210,000; Full time

Job summary

Synopsys Inc. is seeking an accomplished engineer to advance SerDes transceiver models for PAM4 systems targeting PCIe and Ethernet, with a strong emphasis on accuracy and silicon correlation.

You will collaborate with analog, digital, and hardware teams, perform extensive simulations, and design calibration algorithms to push performance while ensuring reliability across channels and protocols.

Qualifications

• M.Sc. or Ph.D. in Electrical or Computer Engineering with 6 to 8+ years of relevant experience.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for PAM4 high-speed serial links.
• Experience with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/system Verilog. Programming in Python is a plus.

Responsibilities

• Developing and maintaining SerDes system models for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.
• Designing and proposing advanced algorithms to calibrate and adapt transceivers for optimal performance.
• Correlating simulated performance with silicon measurements to ensure accuracy and reliability.
• Providing expert assistance to customers for system-level performance issues and troubleshooting.
• Collaborating with cross-functional teams of analog, digital, and hardware engineers throughout all stages of development and post-silicon.
• Contributing to lab testing and analysis for high-speed serial links, ensuring robust design validation.

Job description

Synopsys Inc. is seeking an accomplished engineer to advance SerDes transceiver models for PAM4 systems targeting PCIe and Ethernet, with a strong emphasis on accuracy and silicon correlation.

You will collaborate with analog, digital, and hardware teams, perform extensive simulations, and design calibration algorithms to push performance while ensuring reliability across channels and protocols.