SI/PI Engineer, Advanced Packaging for Optical AI

CScale; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

CScale, a Palo Alto‑based startup, seeks an SI/PI Engineer to own the electrical performance of CspeedIO optical engine packages, guiding modeling and measurement approaches from architecture definition through validation.

Responsibilities include 3D EM modeling, channel analysis, PDN design, and collaboration with CMOS, optical, and packaging teams to converge stack‑up and routing for high‑density designs while ensuring manufacturability and reliability.

Qualifications

• BS or higher in Electrical Engineering, Applied Physics, or a related field, with emphasis on electromagnetics, signal integrity, power integrity, or high-speed digital design.
• 7+ years of package-level SI/PI analysis experience on high-speed interconnects in optical, networking, or high-performance hardware systems.
• Heads-on proficiency with 2.5D/3D EM solvers: Ansys HFSS, SiWave, Cadence Sigrity, CST, or Keysight ADS.
• Command of signal integrity fundamentals, including S-parameter analysis and channel modeling.
• High-speed differential signal integrity at 224G or similar.
• Working knowledge of PCB and package substrate stackup design, via modeling, impedance control, and crosstalk mitigation.
• Working knowledge of power delivery design: decoupling strategy, PDN impedance analysis, and noise mitigation.

Responsibilities

• 3D EM modeling and correlation for high‑speed interconnects.
• Model and characterize in‑package interconnect between IC and photonic dies, including transitions.
• Develop and validate test vehicles to characterize PCB materials, packages, and interconnects.
• Conduct S-parameter and time-domain measurements to extract channel performance and correlate with simulation.
• Define routing constraints, reference plane design, and return path continuity to control degradation.
• Design and optimize PDNs to meet target impedance and minimize noise for high-speed DSPs/ICs.
• Collaborate with CMOS, optical, and packaging teams to converge stack-up and routing strategies.
• Provide SI/PI layout guidelines and support bring-up and validation.

Skills

SI/PI analysis

S-parameter analysis

High-speed SI

Impedance control

Power integrity knowledge

Education

BS or higher in Electrical Engineering, Applied Physics, or a related field

Tools

Ansys HFSS

SiWave

Cadence Sigrity

CST

Keysight ADS

Job description

CScale, a Palo Alto‑based startup, seeks an SI/PI Engineer to own the electrical performance of CspeedIO optical engine packages, guiding modeling and measurement approaches from architecture definition through validation.

Responsibilities include 3D EM modeling, channel analysis, PDN design, and collaboration with CMOS, optical, and packaging teams to converge stack‑up and routing for high‑density designs while ensuring manufacturability and reliability.