Lead FEA Packaging Engineer – Optical ICs

CScale; Palo Alto, Northern (CA, KY); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Cspeed IO in Palo Alto seeks an experienced FEA engineer to drive thermal and structural analysis for optical engine packages. You will build and validate models that influence architecture decisions and qualification, with close collaboration across design, packaging, and suppliers.

The role requires a PhD or MS in engineering, 6+ years of semiconductor packaging FEA, and proficiency in one major FEA/CFD tool plus a second for the complementary domain; experience with 2.5D/3D integration and

Qualifications

• MS or PhD in Mechanical Engineering, Materials Science, Engineering Mechanics, or equivalent practical background.
• 6+ years of finite element analysis for semiconductor packaging or electronic systems, including one product carried from architecture through hardware correlation.
• Expert proficiency in one commercial FEA or CFD tool and working proficiency in a second covering the other domain.
• Sound FEA fundamentals: meshing judgment, boundary conditions, convergence, and defend a model with evidence.
• Demonstrated correlation of simulation against physical measurement.

Responsibilities

• Build and maintain thermal models spanning die, package, interface materials, lid, and cold plate.
• Resolve temperature field and define heat extraction path and interface material selection.
• Predict warpage and manage flatness budgets for assembly and optical coupling.
• Analyze bump/interconnect stress and fatigue life, supporting JEDEC or equivalent.
• Define modeling standards and document assumptions for auditable results.
• Lead correlation against measured temperature, warpage, and reliability data.
• Provide requirements, constraints, and sign-off criteria during architecture definition.
• Engage substrate suppliers, OSATs, and cooling/material vendors on data.

Skills

FEA

Thermal analysis

Education

MS or PhD in Mechanical Engineering, Materials Science, Engineering Mechanics, or equivalent practical background

Tools

Ansys Mechanical

Abaqus

Icepak

Flotherm

Fluent

Celsius

Job description

Cspeed IO in Palo Alto seeks an experienced FEA engineer to drive thermal and structural analysis for optical engine packages. You will build and validate models that influence architecture decisions and qualification, with close collaboration across design, packaging, and suppliers.

The role requires a PhD or MS in engineering, 6+ years of semiconductor packaging FEA, and proficiency in one major FEA/CFD tool plus a second for the complementary domain; experience with 2.5D/3D integration and