Signal & Power Integrity (SI/PI) Engineer – Advanced Packaging

CspeedIO, Inc.; Palo Alto (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

CspeedIO is a Palo Alto-based stealth startup developing next‑generation optical semiconductor solutions for AI infrastructure. We seek an Electronics/SiP expert to own electrical performance of optical engine packages, including SI/PI from die to host ASIC and power delivery across the package.

You will lead 3D EM modeling, correlation, and design guidance, collaborating with CMOS, optical, and packaging teams to achieve manufacturability and reliability in high‑density layouts.

Qualifications

• BS or higher in Electrical Engineering, Applied Physics, or a related field.
• 7+ years of package-level SI/PI analysis experience in optical/high‑speed hardware.

Responsibilities

• Perform 3D EM design and correlation for high‑speed interconnects.
• Define and optimize in‑package interconnect between IC and photonic dies.
• Characterize test vehicles to assess PCB materials, packages, and interconnects.
• Conduct S‑parameter and time‑domain measurements and compare with simulations.
• Collaborate with CMOS, optical, and packaging teams to align stack‑up and routing.

Skills

Signal Integrity

Power Integrity

High‑Speed Design

EM Simulation

Stackup & Routing

Education

BS or higher in Electrical Engineering / related

Tools

Ansys HFSS

SiWave

Cadence Sigrity

CST

Keysight ADS

Job description

CspeedIO is a stealth startup backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.

CspeedIO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.

The Role

This position owns the electrical performance of CspeedIO optical engine packages across three areas: signal integrity between the electronic IC and the photonic dies inside the package; signal integrity across the channel between the CspeedIO package and the host ASIC; and power integrity for the package as a whole. This role defines the modeling and measurement approach as much as it applies one.

You will drive the electrical definition of the package architecture rather than validate a design handed to you after floorplan freeze.

Responsibilities

3D EM modeling and correlation

• Perform 3D EM design and simulation of high-speed interconnects.
• Model and characterize in-package interconnect between the electronic IC and the photonic dies, including transition structures.
• Develop and validate test vehicles to characterize next-generation PCB materials, packages, and interconnects.
• Conduct S-parameter and time-domain measurement to extract channel performance and correlate against simulation.

Channel architecture and standards compliance

• Perform link-level analysis against advanced high-speed standards, and design package substrate stackups, via structures, breakout regions, and connector transitions to meet IEEE, CEI, and MSA compliance.
• Define routing constraints, reference plane design, and return path continuity to hold signal degradation within budget.

Power delivery

• Design and optimize PDNs to meet target impedance, minimize noise coupling, and support fast transient loads for high-speed DSPs and ICs.

Design collaboration and bring-up

• Work with CMOS design, optical, and packaging teams to converge stack-up, breakout, and routing strategy for high-density designs without sacrificing manufacturability or reliability.
• Provide SI/PI layout guidelines to package substrate designers, and review placement and routing on high-speed paths and power domains before release.
• Support bring-up and validation.

Required Qualifications

• BS or higher in Electrical Engineering, Applied Physics, or a related field, with emphasis on electromagnetics, signal integrity, power integrity, or high-speed digital design.
• 7+ years of package-level SI/PI analysis experience on high-speed interconnects in optical, networking, or high-performance hardware systems.
• Hands-on proficiency with 2.5D/3D EM solvers: Ansys HFSS, SiWave, Cadence Sigrity, CST, or Keysight ADS.
• Command of signal integrity fundamentals, including S-parameter analysis and channel modeling.
• High-speed differential signal integrity at 224G or similar.
• Working knowledge of PCB and package substrate stackup design, via modeling, impedance control, and crosstalk mitigation.
• Working knowledge of power delivery design: decoupling strategy, PDN impedance analysis, and noise mitigation.

Preferred Qualifications

• Co-packaged optics or interposer-structure package experience.
• Custom model and workflow development for EM simulation or measurement automation.
• 2.5D/3D package architecture experience extending beyond interconnect‑level SI/PI.
• 448G signaling, or UCIe or similar die-to-die interfaces