Principal IC Package Design Engineer (SI/PI)

Ciena Corporation; Piscataway Township (NJ); On-site; USD 149,000 - 237,000; Full time

Job summary

Ciena Corporation invites applications for an SI/PI Design Engineer to lead the electrical package design for custom in-house photonic, analog, and digital ICs powering next‑generation optical modules.

You will own advanced package selection, BGA configurations and package structures, and oversee layout, verification, and tapeout. Collaboration across teams will optimize silicon floor plans and interposers, with SIWave/HFSS-based simulations guiding decisions.

Qualifications

• BS in Electrical Engineering or Physics.
• 5+ years hands on experience with IC package design.
• Substrate design experience for RF, digital, high speed and mixed signal die.
• Thorough understanding of signal and power integrity fundamentals.

Responsibilities

• Lead the electrical package design for custom ICs used in optical modules.
• Own and drive advanced package selection, BGA configuration and package structure.
• Responsible for package/SIP layout, optimization, design verification and tapeout.
• Interface with cross-functional groups for new product package selection, feasibility analysis and design.
• Work cross-functionally to optimize silicon floor plan, bump and package pin out.
• Simulate and optimize signal/power integrity and RF performance of the package design.
• Interface with CMs and vendors for sourcing existing designs and future development.

Skills

IC package design

Signal integrity

Power integrity

RF/high-speed packaging

Cross-functional coordination

Education

BS in Electrical Engineering or Physics

Tools

APD

SIP

XPD

Cadence

SIWave

HFSS

Job description

Ciena Corporation invites applications for an SI/PI Design Engineer to lead the electrical package design for custom in-house photonic, analog, and digital ICs powering next‑generation optical modules.

You will own advanced package selection, BGA configurations and package structures, and oversee layout, verification, and tapeout. Collaboration across teams will optimize silicon floor plans and interposers, with SIWave/HFSS-based simulations guiding decisions.