Senior VLSI/ASIC Design Architect — Hybrid

HITEC; Sunnyvale (CA); Hybrid; USD 181,000 - 367,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a Sr. Principle VLSI/ASIC Design Engineer in Sunnyvale, CA, with a hybrid work model requiring ~2 days per week in an HPE office.

You will lead architecture, RTL design, and implementation for complex SoC solutions across networking and compute domains. The role demands senior technical leadership, mentorship, and the ability to drive design flows from architecture through synthesis and timing closure.

Qualifications

• Advanced ASIC/VLSI knowledge and RTL design proficiency.
• Proficient in Verilog/SystemVerilog and related HDLs.
• Experience with architecture, microarchitecture and design flows.

Responsibilities

• Lead early-stage ASIC architecture and design exploration for complex SoC applications.
• Define architectural approaches and implementation plans aligned with roadmaps.
• Design, develop, and modify complex RTL blocks and drive synthesis and timing closure.
• Collaborate with cross-functional teams across architecture, hardware, firmware, verification, and software.
• Mentor engineers and provide technical direction across teams.

Skills

RTL design

Verilog/SystemVerilog

ASIC/VLSI

Mentoring

Education

Electrical Engineering

Job description

Hewlett Packard Enterprise is seeking a Sr. Principle VLSI/ASIC Design Engineer in Sunnyvale, CA, with a hybrid work model requiring ~2 days per week in an HPE office.

You will lead architecture, RTL design, and implementation for complex SoC solutions across networking and compute domains. The role demands senior technical leadership, mentorship, and the ability to drive design flows from architecture through synthesis and timing closure.