Senior Verification Engineer – UVM & SoC Validation

NXP Semiconductors

Chandler (AR)

On-site

USD 148,000 - 200,000

Full time

13 days ago
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Job summary

NXP Semiconductors is seeking a design and verification engineer to drive digital verification for mixed-signal designs. You will develop and maintain UVM-based environments, and collaborate with design leaders to ensure complete coverage before tape-out.

Responsibilities include creating regression suites, reporting defects, and supporting top-level simulations. The role requires strong SystemVerilog, UVM, and ASIC verification expertise, with a focus on high-quality verification outcomes.

Qualifications

  • Bachelor’s degree in Electrical Engineering, Electronic Engineering, or Computer Engineering (with related variants such as VLSI or Physics).
  • Five (5) years of progressive, post baccalaureate experience in job offered, Engineer, Design Engineer, Verification Engineer, or closely related field.
  • Experience with UVM, SystemVerilog, and ASIC verification is required.

Responsibilities

  • Perform semiconductor engineering design, development and testing for firm products.
  • Develop the UVM simulation environment and bridge with mixed signal verification.
  • Create and maintain regression test suites, report bugs and propose solutions.
  • Prepare and hold design verification reviews.

Skills

ARM processor
I2C
SPI
SPMI
UART
SOC Testbench
SystemVerilog
UVM Verification
ASIC design verification
C-based test development

Education

Bachelor’s degree in Electrical Engineering, Electronic Engineering, or Computer Engineering (with related variants such as VLSI or Physics)

Job description

NXP Semiconductors is seeking a design and verification engineer to drive digital verification for mixed-signal designs. You will develop and maintain UVM-based environments, and collaborate with design leaders to ensure complete coverage before tape-out.

Responsibilities include creating regression suites, reporting defects, and supporting top-level simulations. The role requires strong SystemVerilog, UVM, and ASIC verification expertise, with a focus on high-quality verification outcomes.

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