Senior Verification Engineer - Digital & Mixed-Signal IP

Broadcom; Irvine (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Annual bonus

Equity grants

Comprehensive benefits package

Job summary

Broadcom's ASIC Products Division is seeking a senior Design Verification Engineer to lead verification planning, test bench development, and coverage closure for complex digital and mixed-signal IP blocks used in ASICs.

The role emphasizes SystemVerilog, UVM, SVA, and advanced verification methodologies, with opportunities to work with emulation platforms and FPGA prototyping. A BS or MS in Electrical/Computer Engineering with 12+ or 10+ years of related experience is required.

Qualifications

• 12+ years of experience in verification concepts and architectures for complex digital and MXS circuits.
• Experience verifying designs at block and system levels.
• Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC).
• Experience debugging RTL and gate-level netlists, analyzing schematics of analog / MXS circuits.
• Experience with SystemVerilog and advanced verification concepts/methodologies (UVM, SVA).
• Demonstrated ability to plan and deploy reusable, scalable verification environments.
• Experience with scripting languages (Perl/Python, Tcl).
• Legal authorization to work in the US.

Responsibilities

• Define verification plans and environment architecture for complex IP blocks.
• Develop test benches, test cases, and coverage closure strategies.
• Debug and analyze RTL and gate-level failures; drive emulation/FPGA prototyping efforts.
• Collaborate with design teams and EDA vendors to optimize verification flows.
• Develop functional models for block, system, and ASIC level verification.

Skills

SystemVerilog

UVM

SVA

Test bench development

Coverage analysis

Debugging

Scripting

Education

BS in Electrical Engineering / Computer Engineering

MS in Electrical Engineering / Computer Engineering

Tools

Synopsys tools

Cadence tools

Mentor tools

Emulation platforms (Palladium, Veloce, Zebu)

Xilinx FPGA tooling

Tcl scripting

Perl/Python

Git

Job description

Broadcom's ASIC Products Division is seeking a senior Design Verification Engineer to lead verification planning, test bench development, and coverage closure for complex digital and mixed-signal IP blocks used in ASICs.

The role emphasizes SystemVerilog, UVM, SVA, and advanced verification methodologies, with opportunities to work with emulation platforms and FPGA prototyping. A BS or MS in Electrical/Computer Engineering with 12+ or 10+ years of related experience is required.