Senior Verification Engineer - Lead Zero-Defect RTL

NXP Semiconductors

Austin (TX)

Presencial

USD 120.000 - 180.000

Jornada completa

14 días+

Una candidatura completa en un minuto

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Descripción de la vacante

NXP Semiconductors in Austin is seeking a Senior Verification Engineer to lead verification for MCU/MPU digital IPs. You will drive a zero-defect mindset, develop testbenches, and mentor a small team while applying formal methods and AI/LLM-based approaches to improve efficiency.

You will define verification plans, develop drivers and monitors, and analyze coverage with a focus on RTL and SVA. Strong debugging and leadership are essential.

Formación

  • BSEE with 5+ years of semiconductor industry experience or
  • MSEE with 3+ years of experience or
  • PhD with 1+ years of experience
  • Knowledge of DDR, PCIe, AMBA (CHI, ACE, AXI) protocols
  • Expertise in Verilog and SystemVerilog; VHDL a plus
  • Experience with OVM/UVM and formal verification methodologies

Responsabilidades

  • Define and execute verification plans
  • Develop and implement verification testbenches
  • Develop testbench components such as drivers, monitors, and scoreboards, leveraging advanced UVM VIPs
  • Develop directed and constrained-random stimulus
  • Analyze RTL, functional coverage, and assertion coverage results
  • Define and develop functional coverage models
  • Develop and maintain SystemVerilog assertions (SVA)
  • Apply formal verification methodologies
  • Demonstrate debugging and root-cause analysis skills
  • Utilize simulation and debug tools efficiently

Conocimientos

Verilog
SystemVerilog
UVM
Formal verification
AI/LLM approaches
Python scripting
Debugging

Educación

BSEE
MSEE
PhD

Herramientas

VHDL
OVM/UVM toolset
Simulation tools

Descripción del empleo

NXP Semiconductors in Austin is seeking a Senior Verification Engineer to lead verification for MCU/MPU digital IPs. You will drive a zero-defect mindset, develop testbenches, and mentor a small team while applying formal methods and AI/LLM-based approaches to improve efficiency.

You will define verification plans, develop drivers and monitors, and analyze coverage with a focus on RTL and SVA. Strong debugging and leadership are essential.

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