R-10066102 Senior Verification Engineer

NXP Semiconductors; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

NXP Semiconductors in Austin is seeking a Senior Verification Engineer to lead verification for MCU/MPU digital IPs. You will drive a zero-defect mindset, develop testbenches, and mentor a small team while applying formal methods and AI/LLM-based approaches to improve efficiency.

You will define verification plans, develop drivers and monitors, and analyze coverage with a focus on RTL and SVA. Strong debugging and leadership are essential.

Qualifications

• BSEE with 5+ years of semiconductor industry experience or
• MSEE with 3+ years of experience or
• PhD with 1+ years of experience
• Knowledge of DDR, PCIe, AMBA (CHI, ACE, AXI) protocols
• Expertise in Verilog and SystemVerilog; VHDL a plus
• Experience with OVM/UVM and formal verification methodologies

Responsibilities

• Define and execute verification plans
• Develop and implement verification testbenches
• Develop testbench components such as drivers, monitors, and scoreboards, leveraging advanced UVM VIPs
• Develop directed and constrained-random stimulus
• Analyze RTL, functional coverage, and assertion coverage results
• Define and develop functional coverage models
• Develop and maintain SystemVerilog assertions (SVA)
• Apply formal verification methodologies
• Demonstrate debugging and root-cause analysis skills
• Utilize simulation and debug tools efficiently

Skills

Verilog

SystemVerilog

UVM

Formal verification

AI/LLM approaches

Python scripting

Debugging

Education

BSEE

MSEE

PhD

Tools

VHDL

OVM/UVM toolset

Simulation tools

Job description

Role Summary

This position is within the MME MCU/MPU Digital IP team.

Job Title: Senior Verification Engineer

Location: Austin

Role Summary

This position is within the MME MCU/MPU Digital IP team.

We develop best-in-class digital IPs for NXP’s automotive and advanced microcontroller businesses, delivering sensor and processing technologies that enable secure, connected vehicles today and autonomous vehicles of the future.

• Drive a “zero-defect” mindset across the verification team
• Provide technical leadership and guidance on complex verification challenges
• Mentor and grow a small team of engineers

Job Responsibility

• Define and execute verification plans
• Develop and implement verification testbenches
• Develop testbench components such as drivers, monitors, and scoreboards, and leverage advanced UVM VIPs
• Develop directed and constrained-random stimulus
• Analyze RTL, functional coverage, and assertion coverage results
• Define and develop functional coverage models
• Develop and maintain SystemVerilog assertions (SVA)
• Apply formal verification methodologies
• Demonstrate strong debugging skills, including failure reproduction and root-cause analysis
• Exhibit strong analytical and problem-solving skills; familiarity with major simulation and debug tools is a plus

Job Qualification

• BSEE with 5+ years of semiconductor industry experience, or
• MSEE with 3+ years of experience, or
• PhD with 1+ years of experience

Technical Skills

• Knowledge of protocols such as DDR, PCIe, AMBA (CHI, ACE, AXI)
• Strong expertise in Verilog, SystemVerilog (VHDL is a plus)
• Experience with OVM/UVM and class-based verification methodologies
• Experience with formal verification methodologies
• Experience leveraging AI/LLM-based approaches to improve engineering efficiency
• Test pattern debugging and validation on simulation and automated test environments
• Scripting in Python, Perl, and UNIX/Linux
• Familiarity with functional and code coverage methodologies

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.