R-10063886 Principal Digital IP Verification Engineer

NXP Semiconductors; Austin (TX); Hybrid; USD 110,000 - 150,000; Full time

Job summary

NXP Semiconductors in Austin, TX, is seeking an experienced candidate for their digital IP team to define and execute verification plans for automotive and microcontroller technologies.

The ideal candidate will possess strong debugging skills and significant industry experience with a focus on delivering secure, connected vehicles. This role offers a hybrid work environment combining in-office and remote work.

Qualifications

• 8+ years of experience in the semiconductor industry for BSEE, or 5+ years for MSEE, or 3+ years for PhD.
• Strong analytical and problem-solving skills.
• Familiarity with major simulation and debug tools.

Responsibilities

• Define and execute verification plans.
• Drive a zero-defect mindset across the verification team.
• Mentor and grow a small team of engineers.

Skills

Knowledge of protocols such as DDR, PCIe, AMBA (CHI, ACE, AXI)

Strong expertise in Verilog, SystemVerilog (VHDL is a plus)

Experience with OVM/UVM and class-based verification methodologies

Experience with formal verification methodologies

Scripting in Python, Perl, and UNIX/Linux

Education

BSEE with 8+ years of semiconductor industry experience

MSEE with 5+ years of experience

PhD with 3+ years of experience

Tools

FPGA/emulation/prototyping platforms (e.g., HAPS, Palladium, Zebu)

Job description

This position is within the MME MCU/MPU Digital IP team. We develop best-in-class digital IPs for NXP’s automotive and advanced microcontroller businesses, delivering sensor and processing technologies that enable secure, connected vehicles today and autonomous vehicles of the future.

Job Summary

• Define and execute verification plans
• Develop and implement verification testbenches
• Develop testbench components such as drivers, monitors, and scoreboards, and leverage advanced UVM VIPs
• Develop directed and constrained-random stimulus
• Analyze RTL, functional coverage, and assertion coverage results
• Define and develop functional coverage models
• Develop and maintain SystemVerilog assertions (SVA)
• Apply formal verification methodologies
• Demonstrate strong debugging skills, including failure reproduction and root-cause analysis
• Exhibit strong analytical and problem-solving skills; familiarity with major simulation and debug tools is a plus

Key Responsibilities

• Drive a “zero-defect” mindset across the verification team
• Provide technical leadership and guidance on complex verification challenges
• Mentor and grow a small team of engineers

Cross-Functional Collaboration

• Partner with local and global SoC and IP teams to drive best practices and continuous productivity improvements
• Demonstrate outstanding problem-solving and analytical capabilities

Qualifications

• BSEE with 8+ years of semiconductor industry experience, or
• MSEE with 5+ years of experience, or
• PhD with 3+ years of experience

Technical Skills

• Knowledge of protocols such as DDR, PCIe, AMBA (CHI, ACE, AXI)
• Strong expertise in Verilog, SystemVerilog (VHDL is a plus)
• Experience with OVM/UVM and class-based verification methodologies
• Experience with formal verification methodologies
• Experience leveraging AI/LLM-based approaches to improve engineering efficiencyTest pattern debugging and validation on simulation and automated test environments
• Scripting in Python, Perl, and UNIX/Linux
• Experience with FPGA/emulation/prototyping platforms (e.g., HAPS, Palladium, Zebu) is a plus
• Understanding of power management concepts
• Familiarity with functional and code coverage methodologies

Location

Austin, TX (Hybrid)

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.