Senior UVM Verification Engineer - FPGA/ASIC

Draper; Cambridge (MA); On-site; USD 82,000 - 220,000; Full time

Job summary

Draper’s Cambridge, MA team is seeking a Senior UVM Digital Verification Engineer to tackle verification challenges in FPGAs and ASICs. You will apply modern verification strategies to complex digital and mixed-signal designs in embedded security, cryptography, signal and image processing, navigation and communications.

The role requires 5–7 years of systems verification experience, strong SystemVerilog/UVM/UVMF, and the ability to lead small teams.

Qualifications

• 5–7 years of systems analysis or related experience.
• Experience integrating descriptive modeling with simulation tools.
• Strong knowledge of SystemVerilog and UVM/UVMF.

Responsibilities

• Develop verification approaches and plans for FPGA/ASIC designs.
• Develop UVM agents for proprietary buses and VIPs for industry standards.
• Lead small engineering teams and mentor junior staff.
• Collaborate with RTL designers to resolve simulation issues and ensure coverage goals.

Skills

SystemVerilog

UVM/UVMF

Verification

Scripting

Education

B.S. in Engineering

M.S. preferred

Tools

Questasim

Xcelium

VCS

Python

Perl

Bash

Job description

Draper’s Cambridge, MA team is seeking a Senior UVM Digital Verification Engineer to tackle verification challenges in FPGAs and ASICs. You will apply modern verification strategies to complex digital and mixed-signal designs in embedded security, cryptography, signal and image processing, navigation and communications.

The role requires 5–7 years of systems verification experience, strong SystemVerilog/UVM/UVMF, and the ability to lead small teams.