Data Fabric Verification Engineer | SystemVerilog & Formal

iFlow Inc.; Sunnyvale (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

iFlow Inc. is seeking a Design Verification Engineer in Sunnyvale, California. This long-term position requires expertise in SystemVerilog and a background in designing verification environments, with at least 5 years of experience and solid RTL design understanding.

The successful candidate will write test sequences, work with engineers for logic verification, and help ensure verification quality metrics are met. A Bachelor's or Master's in Computer or Electrical Engineering is preferred.

Qualifications

• Bachelor's or Master's degree in Computer or Electrical Engineering.
• 5+ years of design verification experience.
• Expertise in SystemVerilog.
• Background in designing verification environments.
• Knowledge of RTL design and formal verification tools.

Responsibilities

• Write test sequences to verify RTL designs.
• Coordinate with design engineers for logic verification.
• Ensure verification quality metrics are met.

Skills

SystemVerilog

Verification environments

RTL design

Formal verification tools

Test sequence writing

Cross-functional coordination

Education

Bachelor's or Master's in Computer or Electrical Engineering

Tools

RTL simulators

Formal verification tools

Job description

iFlow Inc. is looking for a Design Verification Engineer located in Sunnyvale, California. This long-term position requires expertise in System Verilog and a background in designing verification environments. The ideal candidate will have at least 5 years of experience and a strong understanding of RTL design and formal verification tools.

Responsibilities include writing test sequences, coordinating with engineers for logic design verification, and ensuring verification quality metrics are met. A Bachelor's or Master's degree in Computer or Electrical Engineering is preferred.