Senior SystemVerilog Verification Engineer (PCIe)

Infobahn Softworld Inc; Longmont (CO); On-site; USD 82,656 - 110,208; Full time

Job summary

A technology services provider located in Longmont, Colorado, is seeking a Mid-Senior level engineer for contract work in Semiconductor Manufacturing. The candidate should have extensive verification experience with SystemVerilog and be familiar with ASIC and FPGA concepts. Key responsibilities include functional verification of IP and enhancing simulation test environments. Strong debugging skills and ability to communicate effectively are vital for this role.

Qualifications

• 3+ years of verification experience with SystemVerilog for IP or system level verification.
• Familiar with UVM verification methodologies.
• Strong debug skills with simulation tools.

Responsibilities

• Participate in design and functional verification of blocks of IP.
• Develop and improve simulation test environments with directed and constrained-random tests.
• Adopt evolving verification methodologies and work within existing verification infrastructure.

Skills

SystemVerilog

Class-based verification techniques

Simulation tools (VCS, QuestaSim, Xcelium)

ASIC and FPGA concepts

Self-learning ability

Task automation scripting (Python, Bash, etc.)

High speed IO (Ethernet, PCIe, CXL)

Tools

AMD Vivado

Verification IP from Siemens, Cadence, Synopsys

Job description

A technology services provider located in Longmont, Colorado, is seeking a Mid-Senior level engineer for contract work in Semiconductor Manufacturing. The candidate should have extensive verification experience with SystemVerilog and be familiar with ASIC and FPGA concepts. Key responsibilities include functional verification of IP and enhancing simulation test environments. Strong debugging skills and ability to communicate effectively are vital for this role.