Senior ASIC/FPGA Verification Engineer: RTL/UVM Expert

Info-Ways; Milwaukee (WI); On-site; USD 100,000 - 130,000; Full time

Job summary

A leading technology company is seeking an ASIC/FPGA Senior Verification Engineer in Milwaukee, WI or Mayfield Heights, OH. This role involves working on ASIC and FPGA designs, including digital logic design and verification. Candidates should have at least 5 years’ experience, be proficient in Verilog/VHDL, and have a solid understanding of ASIC design methodologies. Strong communication skills in English and the ability to engage in technical discussions are essential. The company offers a competitive rate for this contract position.

Qualifications

• Minimum of 5 years’ experience with standard cell ASIC and FPGA design.
• Familiarity with RTL and gate level design and verification using VHDL and/or Verilog.
• Ability to design independently for medium/high complexity problems.

Responsibilities

• Participate in ASIC/FPGA implementation and verification.
• Create a test specification from the ASIC/FPGA functional specification.
• Implement tests in VHDL/Verilog/System Verilog languages.

Skills

Basic understanding of CMOS ASIC fundamentals

Team Player

Good Communication Skills

Verilog / VHDL

Linux/Unix environment

Education

BE / MS or ME / MTech / MS in Electronics / Electrical Engineering

Job description

A leading technology company is seeking an ASIC/FPGA Senior Verification Engineer in Milwaukee, WI or Mayfield Heights, OH. This role involves working on ASIC and FPGA designs, including digital logic design and verification. Candidates should have at least 5 years’ experience, be proficient in Verilog/VHDL, and have a solid understanding of ASIC design methodologies. Strong communication skills in English and the ability to engage in technical discussions are essential. The company offers a competitive rate for this contract position.