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Job summary
A leading technology firm is seeking an ASIC Verification Engineer in Austin, Texas. This position offers the chance to verify global IP across various products like consumer graphics and AI, collaborating closely with design teams. Candidates should have a BS/MS in Electrical or Computer Engineering and 2+ years of design verification experience, preferably with UVM and SystemVerilog. The role offers a competitive salary range from $116,000 to $189,750, with opportunities for equity and a commitment to diversity.
Qualifications
2+ years of proven design verification experience.
Experience in pre-silicon verification (UVM, SystemVerilog).
Exposure to design and verification tools.
Responsibilities
Develop verification test plans and maintain regressions.
Automate flows for verifying generated RTL.
Collaborate with design teams to resolve verification issues.
Skills
Design verification experience
Programming in Perl or Python
Excellent debugging skills
Collaboration skills
Education
BS/MS in Electrical or Computer Engineering
Tools
UVM
SystemVerilog
VCS
DC Shell
Job description
A leading technology firm is seeking an ASIC Verification Engineer in Austin, Texas. This position offers the chance to verify global IP across various products like consumer graphics and AI, collaborating closely with design teams. Candidates should have a BS/MS in Electrical or Computer Engineering and 2+ years of design verification experience, preferably with UVM and SystemVerilog. The role offers a competitive salary range from $116,000 to $189,750, with opportunities for equity and a commitment to diversity.