Senior PMIC Digital Verification Lead

NXP Semiconductors; Chandler (AZ); Hybride; USD 120 000 - 165 000; Plein temps

Résumé du poste

NXP Semiconductors in Chandler, AZ, is seeking a Senior Digital Verification Engineer to lead verification from architecture through signoff for PMICs used in automotive and industrial applications.

The role requires deep expertise in digital design and verification, including SystemVerilog, UVM, formal methods, and coverage-driven approaches. You will mentor junior engineers and collaborate with global teams on diverse projects.

Qualifications

• Extensive experience in digital verification of PMICs and SoCs.
• Strong knowledge of FSMs, CDC, reset architectures, and low-power design.
• Experience with constrained-random verification, coverage-driven methodology, and regression automation.
• Hands-on verification testbenches, drivers, monitors, and assertions.
• Familiarity with AMBA, I2C, SPI, UART, CAN, DDR, PCIe protocols.

Responsabilités

• Lead digital verification activities and drive successful project execution from planning through signoff.
• Define verification plans, methodologies, environments, regressions, coverage goals, and signoff criteria.
• Review product requirements, architecture specifications, microarchitecture, interfaces, and implementation plans.
• Develop and maintain advanced verification environments using SystemVerilog, UVM, VIPs, scoreboards, monitors, checkers, and assertions.
• Create directed and constrained-random test scenarios to validate functionality, performance, robustness, and corner-case behavior.
• Define, implement, and analyze functional, code, and assertion coverage; drive coverage closure and signoff.
• Apply SystemVerilog Assertions (SVA), formal verification methodologies, and regression analysis to identify and resolve issues.
• Verify PMIC digital control, telemetry, diagnostics, safety, power sequencing, fault management, communication interfaces, and embedded control functions.
• Deliver verification collateral including test plans, environments, assertions, regressions, coverage reports, metrics, milestones, and requirements traceability.
• Drive methodology improvements, automation, reuse, and productivity while mentoring junior engineers and collaborating across global teams.

Connaissances

Strong analytical skills

Problem-solving

Communication

Leadership

Mentoring

Cross-functional collaboration

Debugging

Team leadership

Formation

BSEE

MSEE

PhD

Outils

Verilog

SystemVerilog

UVM

OVM

SVA

Formal verification

UPF/CPF

Python

Perl

Unix/Linux shell scripting

AMBA

I2C

SPI

UART

CAN

LIN

DDR

PCIe

FPGA

emulation

HAPS

Palladium

Zebu

Description du poste

NXP Semiconductors in Chandler, AZ, is seeking a Senior Digital Verification Engineer to lead verification from architecture through signoff for PMICs used in automotive and industrial applications.

The role requires deep expertise in digital design and verification, including SystemVerilog, UVM, formal methods, and coverage-driven approaches. You will mentor junior engineers and collaborate with global teams on diverse projects.