Lead Verification Architect for Automotive IP

Indus Valley Consultants, Inc.; Austin (TX); Sur place; USD 120 000 - 180 000; Plein temps

Résumé du poste

NXP in Austin is seeking a Principal Verification Engineer to drive a zero-defect mindset within the verification team and provide technical leadership across complex challenges.

You will mentor a small team, define verification plans, develop testbenches, and apply both directed and constrained-random stimulus, UVM/VIP techniques, and formal methods to ensure robust digital IP verification for automotive MCUs and sensors.

Qualifications

• BSEE with 5+ years of semiconductor industry experience.
• MSEE with 3+ years of experience.
• PhD with 1+ years of experience.

Responsabilités

• Define and execute verification plans.
• Develop and implement verification testbenches.
• Develop testbench components such as drivers, monitors, and scoreboards, and leverage advanced UVM VIPs.
• Develop directed and constrained-random stimulus.
• Analyze RTL, functional coverage, and assertion coverage results.
• Define and develop functional coverage models.
• Develop and maintain SystemVerilog assertions (SVA).
• Apply formal verification methodologies.
• Demonstrate strong debugging skills, including failure reproduction and root-cause analysis.
• Exhibit strong analytical and problem-solving skills; familiarity with major simulation and debug tools is a plus.

Connaissances

DDR

PCIe

AMBA

Verilog

SystemVerilog

UVM

Formal verification

Python

Perl

UNIX/Linux

AI/LLM

Testbenches

Formation

BSEE

MSEE

PhD

Description du poste

NXP in Austin is seeking a Principal Verification Engineer to drive a zero-defect mindset within the verification team and provide technical leadership across complex challenges.

You will mentor a small team, define verification plans, develop testbenches, and apply both directed and constrained-random stimulus, UVM/VIP techniques, and formal methods to ensure robust digital IP verification for automotive MCUs and sensors.