Senior Design Verification Engineer

ACL Digital; Austin (TX); On-site; USD 115,000 - 190,000; Full time

Job summary

ACL Digital in Austin, TX seeks a Verification Engineer to verify high-speed Ethernet subsystems using SystemVerilog/UVM. You will create testbenches, plans, and coverage models to ensure signoff.

You will integrate Ethernet VIPs, run regressions, debug failures, and work with RTL, Architecture and Post-Silicon teams through verification signoff. Strong SV/UVM and scripting skills required; experience with Ethernet VIPs and SVA is essential.

Qualifications

• Strong SystemVerilog/UVM expertise.
• Hands-on high-speed Ethernet verification experience.
• Experience with Ethernet VIPs, assertions (SVA), constrained-random verification, and functional/code coverage closure.
• Proficiency with Xcelium/VCS/Questa, Verdi debug, and scripting (Python/Perl/Shell).
• Good debugging and communication skills.

Responsibilities

• Verify the high-speed Ethernet subsystem using SystemVerilog/UVM.
• Develop verification plans, testbenches, test cases, assertions, and functional coverage models.
• Integrate Ethernet VIPs, execute regressions, debug test failures, and drive coverage closure to signoff.
• Collaborate with RTL, Architecture, and Post-Silicon Validation teams through verification signoff.

Skills

SystemVerilog/UVM

Ethernet verification

Ethernet VIPs

Scripting languages (Python/Perl/Shell

Debugging & communication

Tools

Verdi

Xcelium/Questa/VCS

Job description

Verify the high-speed Ethernet subsystem using SystemVerilog/UVM.

Develop verification plans, testbenches, test cases, assertions, and functional coverage models.

Integrate Ethernet VIPs, execute regressions, debug test failures, and drive coverage closure to signoff.

Collaborate with RTL, Architecture, and Post-Silicon Validation teams through verification signoff.

Required Skills

• Strong SystemVerilog/UVM expertise.
• Hands-on high-speed Ethernet verification experience.
• Experience with Ethernet VIPs, assertions (SVA), constrained-random verification, and functional/code coverage closure.
• Proficiency with Xcelium/VCS/Questa, Verdi debug, and scripting (Python/Perl/Shell).
• Good debugging and communication skills.