Lead Verification Engineer – DDR6 & SystemVerilog/UVM

Renesas; Tampa (FL); On-site; USD 140,000 - 190,000; Full time

Job summary

Renesas is seeking a Principal Design Verification Engineer to lead verification strategy for next‑generation semiconductor memory interface products, including data buffer silicon. The role emphasizes SystemVerilog/UVM, design verification ownership, and collaboration with RTL/design teams to meet performance and functionality goals.

The candidate will architect and optimize verification environments, drive coverage, and mentor engineers.

Qualifications

• Requires a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Extensive semiconductor design verification experience with ownership of complex verification efforts.
• Expert-level proficiency with SystemVerilog and UVM.

Responsibilities

• Lead verification strategy and execution for complex semiconductor designs at the block and system level.
• Define verification methodologies, test plans, coverage strategies, and verification environments.
• Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and verification environments.
• Drive test development, functional coverage, checkers, constrained‑random verification, and coverage closure.
• Provide technical guidance and mentorship to verification engineers and lead the team to signoff.

Skills

SystemVerilog

UVM

Verification strategies

Test plans

Debugging

Mentoring

Technical leadership

DDR memory experience

Education

Bachelor's or Master's in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

UVM environments

DDR memory interfaces

Job description

Renesas is seeking a Principal Design Verification Engineer to lead verification strategy for next‑generation semiconductor memory interface products, including data buffer silicon. The role emphasizes SystemVerilog/UVM, design verification ownership, and collaboration with RTL/design teams to meet performance and functionality goals.

The candidate will architect and optimize verification environments, drive coverage, and mentor engineers.