Principal Design Verification Engineer - DDR6/UVM Lead

Renesas; Melbourne (FL); On-site; USD 140,000 - 190,000; Full time

Job summary

Renesas in the United States is seeking a Principal Design Verification Engineer to lead verification strategy and execution for memory interface products, including data buffer silicon. The role focuses on SystemVerilog/UVM testbenches, block- and system-level verification, and ownership from planning through signoff.

The ideal candidate has deep semiconductor verification expertise, DDR memory experience is a plus, and a track record of mentoring verification engineers and driving coverage

Qualifications

• Bachelor's or Master's degree in Electrical/ Computer Engineering or related field.
• Extensive semiconductor design verification experience with ownership.
• Expert-level proficiency with SystemVerilog.
• Strong UVM experience including building verification environments.
• Experience defining verification strategies.
• DDR/memory experience a plus.

Responsibilities

• Lead verification strategy and execution for complex semiconductor designs at block and system level.
• Define verification methodologies, test plans, coverage strategies, and environments.
• Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and environments.
• Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure.
• Take ownership of verification from planning through signoff.
• Collaborate with RTL/design teams to ensure verifiable designs.

Skills

SystemVerilog

UVM

DDR/memory

Leadership

Testbench

Education

Electrical/Computer Engineering (B.S./M.S.)

Tools

UVM tools

Verilog/SystemVerilog

Job description

Renesas in the United States is seeking a Principal Design Verification Engineer to lead verification strategy and execution for memory interface products, including data buffer silicon. The role focuses on SystemVerilog/UVM testbenches, block- and system-level verification, and ownership from planning through signoff.

The ideal candidate has deep semiconductor verification expertise, DDR memory experience is a plus, and a track record of mentoring verification engineers and driving coverage