Senior ASIC Verification Engineer – SoC/IP

Meta

Menlo Park (CA)

On-site

USD 146,000 - 209,000

Full time

17 hours ago
Be an early applicant
Application generator

Stand out for this role — generate a tailored resume and cover letter in about a minute.

Get past ATS filters

Benefits offered by this job

Bonus
Equity
Benefits

Job summary

Meta is hiring an ASIC Design Verification Engineer to build IP and SoC verification for data center applications. You will define verification plans, develop test benches, and drive closure using coverage metrics, collaborating with Design, Model, Emulation and Silicon teams to ensure first-pass silicon success.

The role emphasizes SystemVerilog/UVM, C/C++ verification skills, and scripting with Python/TCL/Perl.

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience.
  • 6+ years hands-on experience in SystemVerilog/UVM or C/C++ verification.
  • 6+ years of IP/sub-system and/or SoC verification using SystemVerilog UVM/OVM.
  • Experience with EDA tools and scripting (Python, TCL, Perl, Shell) for verification tooling.

Responsibilities

  • Define and implement IP/SoC verification plans and build test benches for verification at IP/sub-system/SoC level.
  • Develop functional tests based on the verification plan.
  • Push design verification to closure using defined metrics, coverage, and tests.
  • Debug and root-cause functional failures in collaboration with the Design team.
  • Collaborate with cross-functional teams (Design, Model, Emulation, Silicon validation) to ensure quality.
  • Advance verification infrastructure using the latest methodologies and tools.

Skills

SystemVerilog/UVM
C/C++ verification
Python scripting
Formal methods

Education

Bachelor's degree in CS/CE or equivalent

Tools

Python
TCL
Perl
Shell

Job description

Meta is hiring an ASIC Design Verification Engineer to build IP and SoC verification for data center applications. You will define verification plans, develop test benches, and drive closure using coverage metrics, collaborating with Design, Model, Emulation and Silicon teams to ensure first-pass silicon success.

The role emphasizes SystemVerilog/UVM, C/C++ verification skills, and scripting with Python/TCL/Perl.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Staff ASIC Verification Architect (SoC/IP) – UVM Expert
Staff ASIC Verification Architect (SoC/IP) – UVM Expert

Meta • Sunnyvale (CA)

On-site
USD 178,000 - 250,000
Bonus
Equity
Benefits
Senior ASIC Verification Engineer - SystemC/C++ & UVM Lead
Senior ASIC Verification Engineer - SystemC/C++ & UVM Lead

Insight Global • North Reading (MA)

On-site
USD 154,000 - 307,000
Staff ASIC Verification Engineer for AI/Data Center
Staff ASIC Verification Engineer for AI/Data Center

Meta • Sunnyvale (CA)

On-site
USD 178,000 - 250,000
ASIC Verification Engineer
ASIC Verification Engineer

Links Technology Solutions, Inc. • Carlsbad (CA)

On-site
USD 96,000 - 110,000
Health insurance
Life insurance
Vision insurance
+2
ASIC Verification Engineer: 26-02766
ASIC Verification Engineer: 26-02766

Akraya, Inc. • Allentown

On-site
USD 96,000 - 99,000
ASIC Engineer, Design Verification
ASIC Engineer, Design Verification

Meta • Sunnyvale (CA)

On-site
USD 178,000 - 250,000
Bonus
Equity
Benefits
ASIC Engineer, Design Verification
ASIC Engineer, Design Verification

Meta • Menlo Park (CA)

On-site
USD 146,000 - 209,000
Bonus
Equity
Benefits
Senior ASIC Verification Lead - SystemC/C++ & SystemVerilog
Senior ASIC Verification Lead - SystemC/C++ & SystemVerilog

Insight Global • North Reading (MA)

On-site
USD 140,000 - 190,000
Principal Engineer - ASIC Verification
Principal Engineer - ASIC Verification

Nokia • San Jose (CA)

On-site
USD 130,000 - 160,000
Senior ASIC Verification Engineer – SystemVerilog/UVM
Senior ASIC Verification Engineer – SystemVerilog/UVM

Socket.dev • San Diego (CA)

On-site
USD 116,000 - 173,000