Senior UCIe Post-Silicon Validation Lead

Synopsys Inc; Hillsboro (OR); On-site; USD 180,000 - 280,000; Full time

Job summary

Synopsys Inc. seeks an experienced engineering leader to guide a team of validation and characterization engineers focused on UCIe die-to-die interface IP. You will own end-to-end silicon testchip characterization and drive critical customer bring-up activities.

You will manage budgets, headcount, and lab investments while shaping standards for measurement, data correlation, and sign-off processes. A hands-on, technically credible leader is essential.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering with 10+ years of related experience.
• Demonstrated people management experience in a silicon or hardware engineering organization.
• Extensive hands-on background in post-silicon characterization, validation, and debug of high-speed mixed-signal interface IP.
• Familiarity with the UCIe specification and the die-to-die ecosystem, including PHY and D2D adapter layers.

Responsibilities

• Lead and directly manage a team of validation and characterization engineers supporting UCIe-based die-to-die interface IP, including hiring and performance management.
• Own the characterization and validation of internal silicon testchips end to end from plan definition to silicon sign-off.
• Own the customer silicon bring up and debug mission, including on-site lab engagement.
• Oversee resources to meet schedules and goals, balancing internal testchip programs with customer commitments.
• Establish standards and methodologies for characterization execution and silicon sign-off criteria.

Skills

Leadership

People Management

Communication

Budgeting

Strategic Planning

Cross-functional Collaboration

Education

Bachelor's in Electrical or Computer Engineering

Advanced degree in Electrical or Computer Engineering

Tools

Python

C

C++

Oscilloscopes

BERTs

Spectrum Analyzers

Job description

Synopsys Inc. seeks an experienced engineering leader to guide a team of validation and characterization engineers focused on UCIe die-to-die interface IP. You will own end-to-end silicon testchip characterization and drive critical customer bring-up activities.

You will manage budgets, headcount, and lab investments while shaping standards for measurement, data correlation, and sign-off processes. A hands-on, technically credible leader is essential.