Post-Silicon Validation Lead, UCIe Die-to-Die

Synopsys, Inc.; Hillsboro (OR); Presencial; USD 180.000 - 240.000; Jornada completa

Descripción de la vacante

Synopsys, Inc. is seeking a senior post-silicon validation engineer to own the die-to-die IP verification for UCIe interfaces.

You will lead the evaluation and sign-off of silicon readiness, coordinating across analog, digital, and packaging teams to resolve complex issues. You will develop and maintain validation frameworks in Python, manage lab automation, and drive cross-function programs focused on silicon quality and data integrity.

Formación

• Bachelor's degree in Electrical Engineering or Computer Engineering with 10+ years of related experience, or an advanced degree with 8 years of related experience.
• Extensive expertise in post-silicon validation, characterization, and debug of high-speed mixed-signal interface IP across multiple silicon generations and process nodes.
• Authoritative command of the UCIe specification, including PHY and D2D layers, link training, sideband operation, and packaging tradeoffs; direct UCIe or other die-to-die experience is preferred.

Responsabilidades

• Define the post-silicon validation strategy for UCIe-based die-to-die IP, including methodology, coverage models, and sign-off criteria.
• Act as final technical escalation point for silicon issues requiring cross-domain evaluation.
• Lead bring-up and debugging of customer silicon, remotely or on-site in labs.
• Own the architecture of the validation software platform in Python, with lab automation frameworks and data infrastructure.
• Coordinate validation programs across analog, digital, firmware, product engineering, applications, and marketing.

Conocimientos

Post-silicon validation

UCIe specification

High-speed SerDes

Python

Lab automation

Oscilloscopes

BERTs

GitLab

Jira/Confluence

Educación

Bachelor's degree in Electrical Engineering or Computer Engineering

Advanced degree with 8+ years

Herramientas

GitLab

Jira

Confluence

Descripción del empleo

Synopsys, Inc. is seeking a senior post-silicon validation engineer to own the die-to-die IP verification for UCIe interfaces.

You will lead the evaluation and sign-off of silicon readiness, coordinating across analog, digital, and packaging teams to resolve complex issues. You will develop and maintain validation frameworks in Python, manage lab automation, and drive cross-function programs focused on silicon quality and data integrity.