Post-Silicon Validation, Senior Manager

Synopsys Inc; Hillsboro (OR); On-site; USD 180,000 - 280,000; Full time

Job summary

Synopsys Inc. seeks an experienced engineering leader to guide a team of validation and characterization engineers focused on UCIe die-to-die interface IP. You will own end-to-end silicon testchip characterization and drive critical customer bring-up activities.

You will manage budgets, headcount, and lab investments while shaping standards for measurement, data correlation, and sign-off processes. A hands-on, technically credible leader is essential.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering with 10+ years of related experience.
• Demonstrated people management experience in a silicon or hardware engineering organization.
• Extensive hands-on background in post-silicon characterization, validation, and debug of high-speed mixed-signal interface IP.
• Familiarity with the UCIe specification and the die-to-die ecosystem, including PHY and D2D adapter layers.

Responsibilities

• Lead and directly manage a team of validation and characterization engineers supporting UCIe-based die-to-die interface IP, including hiring and performance management.
• Own the characterization and validation of internal silicon testchips end to end from plan definition to silicon sign-off.
• Own the customer silicon bring up and debug mission, including on-site lab engagement.
• Oversee resources to meet schedules and goals, balancing internal testchip programs with customer commitments.
• Establish standards and methodologies for characterization execution and silicon sign-off criteria.

Skills

Leadership

People Management

Communication

Budgeting

Strategic Planning

Cross-functional Collaboration

Education

Bachelor's in Electrical or Computer Engineering

Advanced degree in Electrical or Computer Engineering

Tools

Python

C

C++

Oscilloscopes

BERTs

Spectrum Analyzers

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the lab, oscilloscope probes in hand, hunting down signal integrity issues that make the difference between a chiplet link that trains and one that does not. Managing people came later, but you never stopped being an engineer first. You know what good characterization data looks like because you have collected it yourself, and you can tell when a measurement setup is lying to you before anyone else in the room notices.

Leading a team means you care as much about building the methodology as hitting the milestone. You think about how to make the next testchip bring up faster than the last one, not just whether it passed. When a customer calls with a silicon issue, you are the person who can triage it in real time, decide whether to send someone on-site, and explain the risk to leadership without sugarcoating it.

You have managed budgets, headcount, and lab equipment purchases. You have hired engineers and coached them through career pivots. You understand that the hardest part of this job is not the technical depth, it is making sure the right work happens at the right time with the right people, even when three programs need the same engineer next week.

At Synopsys, you will own the silicon data behind UCIe IP releases and the customer relationships that depend on it being right.

What You'll Be Doing

• Lead and directly manage a team of validation and characterization engineers supporting UCIe-based die-to-die interface IP, including hiring, performance management, goal setting, and career development
• Own the characterization and validation of internal silicon testchips end to end, from characterization plan definition through data collection, correlation to simulation and design intent, datasheet parameter confirmation, and silicon sign-off
• Own the customer silicon bring up and debug mission, including sideband and mainband link training, lane repair and reversal, degraded mode operation, and chiplet interoperability, delivered through remote and sometimes on-site lab engagement
• Oversee operational and functional objectives for the group and allocate personnel resources to meet schedules and goals, balancing internal testchip programs against customer commitments that arrive with little notice
• Exercise responsibility for costs, methods, and staffing, including headcount planning, lab capital equipment investment, and the build versus buy decisions behind validation infrastructure and automation
• Establish the standards and methodologies governing characterization execution, measurement and correlation practice, silicon sign-off criteria, and customer lab engagement
• Own the escalation path for critical silicon issues, ensuring the right technical depth is applied and that program and customer risk is communicated early and accurately

The Impact You Will Have

• Own the silicon data behind Synopsys' UCIe die-to-die interface IP release decisions, enabling the multi-die and chiplet-based systems our customers are building
• Deliver operational results that directly affect department targets, including sign-off schedules, silicon respin avoidance, and time-to-market for new IP
• Ensure every testchip yields the characterization data the business needs the first time, rather than discovering gaps after the lab window has closed
• Ensure customer silicon comes up quickly and field issues are resolved before they elevate, protecting both customer launches and Synopsys' technical reputation
• Allocate the people, lab capacity, and equipment investment that determine what the organization is capable of characterizing
• Build a team whose depth and methodology outlast any single program or silicon generation
• Shape how the business approaches characterization of next-generation UCIe data rates, packaging technologies, and chiplet topologies

What You'll Need

• Bachelor's degree in Electrical or Computer Engineering with a minimum of 10 years of related experience, or an advanced degree with a minimum of 8 years of related experience
• Demonstrated people management experience in a silicon or hardware engineering organization, including hiring, performance management, and technical career development
• Extensive hands-on background in post-silicon characterization, validation, and debug of high-speed mixed-signal interface IP, with working knowledge across several related areas such as analog and digital design, firmware, packaging, or product engineering
• Working knowledge of the UCIe specification and the die-to-die ecosystem, including PHY and D2D adapter layers, link training, and standard versus advanced packaging tradeoffs; deep high-speed SerDes background is applicable
• Experience owning R&D lab operations, including capital equipment planning and the high-speed instrumentation used for characterization: oscilloscopes, BERTs, spectrum analyzers, and network analyzers
• Familiarity with validation software and automation development practice across Python, C, and C++, sufficient to set direction and evaluate technical tradeoffs
• Proven track record engaging major customers on technical matters, including silicon bring up support and issue escalation

Who You Are

• A leader who applies extensive knowledge of characterization and validation, plus several related engineering areas, to decisions that affect the whole program
• A hands-on engineering manager who has done the lab work and has not lost the instinct for it
• An operator who can hold schedule, cost, and staffing accountable at the same time without losing technical credibility
• A clear communicator who can brief senior management on risk honestly and early, and influence others in sensitive situations
• A trusted counterpart for major customers, able to negotiate on matters of significance while protecting the technical truth
• A developer of engineers who invests in methodology, tooling, and people so that capability compounds

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards And Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.