Senior Timing Methodology Lead – STA & AI-Driven Flows

Altera; San Jose (CA); On-site; USD 187,000 - 270,000; Full time

Job summary

Altera seeks a senior Design Automation timing lead to drive the architecture of static timing analysis flows and timing modeling across ASIC, IP designs, and FPGA timing deliverables. You will own the methodology, guide a small expert team, and coordinate with design, physical design, and EDA vendors to push greenfield modernization and robust turnouts.

Responsibilities include building production‑grade DA/CAD flows, triaging live tape‑outs, mentoring engineers, and shaping roadmaps for

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 10+ years in semiconductor design automation, CAD/EDA engineering, ASIC/custom IC design, or related field with hands‑on production design automation experience.
• 10+ years with Static Timing Analysis (STA) and timing sign‑off methodology including MCMM, crosstalk, OCV, derates.
• 10+ years with industry‑standard timing analysis, cell characterization, and SPICE tools with deep tool evaluation.
• 10+ years building automation and software for engineering workflows; strong Python, Tcl, shell scripting.
• Experience releasing production‑grade DA/CAD flows including regression, deployment, and support.
• Technical leadership in design automation or timing domain; mentor engineers.
• Experience partnering with ASIC/custom IC physical design and tape‑out support.
• Experience leading cross‑functional technical initiatives across distributed teams.

Responsibilities

• Develop and release production‑grade timing flows and associated regressions.
• Triage timing issues and debug with designers on live tape‑outs.
• Mentor engineers and set methodology direction for timing and DA.

Skills

STA expertise

timing sign-off

leadership

cross-functional collaboration

Python

Tcl

shell scripting

production‑grade Flow development

debugging timing issues

communication with vendors

Education

Bachelor's degree in Electrical/Computer Engineering or related

Master's or PhD in Electrical/Computer Engineering or related

Tools

Python

Tcl

Shell scripting

SPICE circuit simulation tools

Liberty model generation

ECAD/EDA tools

timing methodology tooling

Job description

Altera seeks a senior Design Automation timing lead to drive the architecture of static timing analysis flows and timing modeling across ASIC, IP designs, and FPGA timing deliverables. You will own the methodology, guide a small expert team, and coordinate with design, physical design, and EDA vendors to push greenfield modernization and robust turnouts.

Responsibilities include building production‑grade DA/CAD flows, triaging live tape‑outs, mentoring engineers, and shaping roadmaps for