Senior Tech PM, ASIC/SoC Design – Global Tape-Out Lead

CoAsia SEMI USA; San Jose (CA); On-site; USD 120,000 - 150,000; Full time

Benefits offered by this job

Medical, Dental, and Vision Coverage

401(k) Retirement Plan with Company Matching

Paid Time Off (PTO)

Company Holidays

Collaborative and Global Team Environment

Career Growth Opportunities

Job summary

CoAsia SEMI USA is seeking a Technical Program Manager in San Jose, CA. This full-time role involves managing the lifecycle of ASIC/SoC design projects and serving as the bridge between customers and engineering teams. You'll lead complex development programs from initial architecture to mass production.

The ideal candidate will have over 7 years of semiconductor experience and a deep understanding of the design flow. Benefits include medical coverage, 401(k) matching, and opportunities for career growth within a global team.

Qualifications

• 7+ years of experience in the semiconductor industry managing high-performance SoC projects.
• Deep understanding of the RTL-to-GDSII flow, including timing closure and physical verification.
• Hands-on experience with FinFET/GAA processes and advanced packaging technologies.

Responsibilities

• Lead the end-to-end execution of ASIC design projects.
• Act as the main point of contact for customers and partners.
• Develop detailed project timelines and allocate resources across teams.
• Identify technical bottlenecks and implement contingency plans.
• Moderate technical discussions regarding PPA trade-offs.
• Manage project budgets and invoicing milestones.

Skills

Communication

Leadership

Project Management

Technical Expertise

Education

B.S. or M.S. in Electrical Engineering or related field

Tools

Jira

Confluence

Microsoft Project

Job description

CoAsia SEMI USA is seeking a Technical Program Manager in San Jose, CA. This full-time role involves managing the lifecycle of ASIC/SoC design projects and serving as the bridge between customers and engineering teams. You'll lead complex development programs from initial architecture to mass production.

The ideal candidate will have over 7 years of semiconductor experience and a deep understanding of the design flow. Benefits include medical coverage, 401(k) matching, and opportunities for career growth within a global team.