Senior Substrate & Advanced Packaging Engineer (3DIC)

TSMC - Taiwan Semiconductor Manufacturing Company Limited; San Jose (CA); On-site; USD 154,000 - 250,000; Full time

Job summary

TSMC seeks a seasoned Substrate / Advanced Package Engineer to advance 3DIC packaging and CoWoP initiatives. You will leverage a strong foundation in semiconductor physics, mechanical engineering, and EDA tooling to drive design, simulation, and modeling of complex substrate technologies.

The role emphasizes solving warpage and thermal challenges, collaborating across teams, and delivering documentation for design reviews and project milestones.

Qualifications

• Master's degree or Ph.D. in Electrical Engineering, Mechanical Engineering, or related field.
• 15+ years of hands-on expertise in advanced packaging technologies and substrate design.
• Understanding of semiconductor device physics and packaging process technologies.
• Strong knowledge of warpage, stress, and thermal effects in packaging.
• Proven ability to drive solutions in ambiguous, research-oriented contexts.
• Excellent problem-solving, analytical, and communication skills.
• Strong collaboration skills, with the ability to mentor junior engineers.
• Ability to balance strategic insight with hands-on technical execution.

Responsibilities

• Design, simulate, and optimize advanced packaging for 3DIC applications.
• Collaborate with cross-functional teams to define specifications and requirements.
• Perform modeling of warpage, stress, reliability, and thermal performance using industry-standard EDA tools.
• Formulate and solve problems in research-driven, often ambiguous domains.
• Provide guidance on high-speed I/O modeling and integration.
• Develop and maintain documentation, including specifications, test plans, and design reviews.

Skills

Advanced packaging

Substrate design

3DIC

EDA tools

Warpage analysis

Thermal modeling

High-speed I/O

Cross-functional collaboration

Mentoring

Education

Master's or Ph.D. in EE/ME

Tools

EDA tools

Job description

TSMC seeks a seasoned Substrate / Advanced Package Engineer to advance 3DIC packaging and CoWoP initiatives. You will leverage a strong foundation in semiconductor physics, mechanical engineering, and EDA tooling to drive design, simulation, and modeling of complex substrate technologies.

The role emphasizes solving warpage and thermal challenges, collaborating across teams, and delivering documentation for design reviews and project milestones.