Substrate / Advanced Package Engineer (7103)

TSMC; San Jose (CA); On-site; USD 153,500 - 250,000; Full time

Benefits offered by this job

Comprehensive benefits

Market-competitive pay

Extensive development opportunities

Job summary

TSMC is seeking a highly skilled Substrate / Advanced Package Engineer to join our 3DIC design team in San Jose, CA. The role involves design, simulation, and modeling of complex substrate and packaging technologies. Ideal candidates will have a Master’s or Ph.D. and 15+ years of experience in semiconductor physics and advanced packaging technologies.

With responsibilities including optimization and collaboration across teams, this position offers a competitive salary ranging from $153,500 to $250,000 annually, alongside comprehensive benefits and career development opportunities.

Qualifications

• 15+ years of hands-on expertise in advanced packaging technologies and substrate design.
• Strong knowledge of warpage, stress, and thermal effects in packaging.
• Proven ability to drive solutions in ambiguous, research-oriented contexts.

Responsibilities

• Design, simulate, and optimize advanced packaging for 3DIC applications.
• Collaborate with cross-functional teams to define specifications and requirements.
• Perform modeling of warpage, stress, reliability, and thermal performance.

Skills

Advanced packaging technologies

Semiconductor physics

Mechanical engineering principles

EDA tools

Problem-solving

Collaboration

Education

Master’s degree or Ph.D. in Electrical Engineering or Mechanical Engineering

Job description

Context

As chip sizes increase and packaging technologies become more complex, substrate engineering is emerging as a critical domain. This role supports TSMC’s leadership in 3DIC and advanced packaging by extending expertise beyond chip-level design into package-level integration, addressing challenges such as warpage, power delivery, thermal management, and material innovation. Future evolution includes Chip-on-Wafer-on-PCB (CoWoP) under TSMC’s System Technology Optimization program.

Overview

We are seeking a highly skilled and motivated Substrate / Advanced Package Engineer to join our cutting‑edge 3DIC design team. The ideal candidate will have a strong foundation in semiconductor physics, mechanical engineering principles, and EDA tools, with a passion for innovation in advanced package design. The role involves design, simulation, and modeling of complex substrate and packaging technologies to support next‑generation 3DIC applications.

Responsibilities

• Design, simulate, and optimize advanced packaging for 3DIC applications.
• Collaborate with cross‑functional teams to define specifications and requirements.
• Perform modeling of warpage, stress, reliability, and thermal performance using industry‑standard EDA tools.
• Formulate and solve problems in research‑driven, often ambiguous domains.
• Provide guidance on high‑speed I/O modeling and integration.
• Develop and maintain documentation, including specifications, test plans, and design reviews; stay current with industry trends, tools, and technologies in advanced packaging.

Requirements

• Master’s degree or Ph.D. in Electrical Engineering, Mechanical Engineering, or a related field.
• 15+ years of hands‑on expertise in advanced packaging technologies and substrate design.
• Understanding of semiconductor device physics and packaging process technologies.
• Strong knowledge of warpage, stress, and thermal effects in packaging.
• Proven ability to drive solutions in ambiguous, research‑oriented contexts.
• Excellent problem‑solving, analytical, and communication skills.
• Strong collaboration skills, with the ability to mentor junior engineers.
• Ability to balance strategic insight with hands‑on technical execution.

Preferred Skills

• Experience with reliability, IR/EM, and multi‑physics analysis.
• Familiarity with machine learning techniques for design optimization.
• Patents, publications, or demonstrated innovation in substrate or packaging domains.

Success Metrics

• Ability to provide impactful, data‑driven suggestions that influence design direction.
• Effective use of modeling and simulation to validate proposals.
• Establishing trust and credibility with global teams.
• Enabling adoption of new technologies within the 3DIC ecosystem.

Location

• San Jose, CA or Hsinchu, Taiwan.

Pay Transparency / Benefits

At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $153,500 and $250,000 per year. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience, and the position level and location. TSMC’s total compensation package consists of market‑competitive pay, allowances, bonuses, and comprehensive benefits, and we also offer extensive development opportunities and programs.

Diversity Statement

TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law. TSMC is an equal‑opportunity employer with a strong commitment to diversity and inclusion, and we are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or recruiting process, please notify us at [e-mail]. TSMC confirms its commitment to meet all applicable employment law obligations and to determine reasonable accommodations on a case‑by‑case basis.