Senior Standard Cell Design Methodology & Flows Engineer

Socket.dev; San Diego (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Socket.dev is seeking an experienced IC design engineer to help drive cutting‑edge processor design in deep submicron technologies. You will work with a team on custom circuits, interface with CAD and foundry, and implement Verilog/SystemVerilog blocks while running simulations.

The role emphasizes data analysis and ML to study timing, power, and area trends and to support QA across large datasets. A strong background in library characterization and EDA flows is required.

Qualifications

• BS and 10+ years of relevant industry experience.
• Strong expertise in library characterization, timing, and power analysis.
• Familiarity with EDA tools for characterization, synthesis, place‑route, and verification.

Responsibilities

• Interface with internal CAD team for production flows and foundry PDK requirements.
• Collaborate with technology team on process requirements and enable tool/flow automation.
• Implement digital blocks in Verilog/SystemVerilog and perform simulations or formal checks.
• Apply data analysis and ML models to circuit timing, power, and area trends.

Skills

Verilog/SystemVerilog

Python

Data analysis / ML

Timing/Power/CCS modeling

DFT/RTL

Scripting (Python/Tcl/Perl)

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Spice Simulation

Liberty Formats

Synthesis/Place-Route tools

DFT tools

Job description

Socket.dev is seeking an experienced IC design engineer to help drive cutting‑edge processor design in deep submicron technologies. You will work with a team on custom circuits, interface with CAD and foundry, and implement Verilog/SystemVerilog blocks while running simulations.

The role emphasizes data analysis and ML to study timing, power, and area trends and to support QA across large datasets. A strong background in library characterization and EDA flows is required.