Senior Physical Design Engineer - Advanced-Node ICs

Capgemini; Santa Clara (CA); On-site; USD 82,000 - 193,000; Full time

Benefits offered by this job

Paid time off

Medical coverage

Retirement plans

Life insurance

Employee assistance programs

Job summary

Capgemini Engineering in Santa Clara, CA is seeking a Senior Physical Design Engineer to drive complex digital and mixed-signal IC implementations from floor planning through tape-out. You will collaborate with cross-functional teams, optimize power and area, and ensure robust verification using LVS/DRC and timing analyses.

The role emphasizes experience with advanced node design flows, including clocking strategies and parasitic-aware simulations, across 3nm–7nm technologies.

Qualifications

• 10+ years of Physical Design experience in digital or mixed-signal ICs.
• Strong floor planning, placement, routing, clock tree synthesis, and physical-aware synthesis.
• Experience with power-grid strategies and high-speed clock constraints.
• Familiarity with LVS/DRC, CDC, STA, and parasitic-aware simulations.
• Exposure to mixed-signal environments and tape-out processes.

Responsibilities

• Lead or support physical design activities from floor planning to tape-out.
• Develop power-grid strategies and clock constraints to meet performance/area goals.
• Perform LVS/DRC verification and debug at chip and block levels.
• Collaborate with design, layout, verification, timing, and methodology teams.
• Support timing closure and CDC analyses using EDA tools.
• Contribute to tape-out readiness and foundry interactions.
• Evaluate trade-offs between power, area, and performance for advanced nodes.

Skills

Physical design

Floor planning

Place & route

Clock tree synthesis

Power-grid design

LVS/DRC debugging

Timing analysis

Mixed-signal exposure

EDA tools

Tools

Virtuoso

Calibre

RedHawk

Job description

Capgemini Engineering in Santa Clara, CA is seeking a Senior Physical Design Engineer to drive complex digital and mixed-signal IC implementations from floor planning through tape-out. You will collaborate with cross-functional teams, optimize power and area, and ensure robust verification using LVS/DRC and timing analyses.

The role emphasizes experience with advanced node design flows, including clocking strategies and parasitic-aware simulations, across 3nm–7nm technologies.