Standard Cell Design Methodology & Flow Engineer

Socket.dev; San Diego (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Socket.dev is seeking an experienced IC design engineer to help drive cutting‑edge processor design in deep submicron technologies. You will work with a team on custom circuits, interface with CAD and foundry, and implement Verilog/SystemVerilog blocks while running simulations.

The role emphasizes data analysis and ML to study timing, power, and area trends and to support QA across large datasets. A strong background in library characterization and EDA flows is required.

Qualifications

• BS and 10+ years of relevant industry experience.
• Strong expertise in library characterization, timing, and power analysis.
• Familiarity with EDA tools for characterization, synthesis, place‑route, and verification.

Responsibilities

• Interface with internal CAD team for production flows and foundry PDK requirements.
• Collaborate with technology team on process requirements and enable tool/flow automation.
• Implement digital blocks in Verilog/SystemVerilog and perform simulations or formal checks.
• Apply data analysis and ML models to circuit timing, power, and area trends.

Skills

Verilog/SystemVerilog

Python

Data analysis / ML

Timing/Power/CCS modeling

DFT/RTL

Scripting (Python/Tcl/Perl)

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Spice Simulation

Liberty Formats

Synthesis/Place-Route tools

DFT tools

Job description

Description

Imagine yourself at the center of our cutting-edge processor design in deep submicron technologies, and on standard cell library designs. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of talent engineers. In this role on our custom circuits team, you will:

• Be the interface to internal CAD team for planning production flows and with foundry on PDK requirements.


• Collaborate with technology team on new process requirements and work with design/CAD team to enable relevant tools/flows


• Implement sophisticated digital block in Verilog/SystemVerilog, run simulations or formal check for verification.


• Use data analysis techniques and/or sophisticated Machine Learning models to study the circuit trends in timing, power, and area, and to potentially detect quality issues in large datasets.

Minimum Qualifications

BS and a minimum of 10 years of relevant industry experience

Preferred Qualifications

At least 5+ years in Library Characterization, Timing/Power/CCS Noise/Variation Modeling, Liberty Formats, Spice simulation, Static Timing and Power Analysis flows, etc. Experience with timing modeling of large custom macros and complex sequential flops.Exposure to Design For Test, scan concept and write DFT friendly RTLUnderstands all aspects of implementation specification, design, timing, power, and flow automation.Data analysis and ML knowledge to study data trend and perform QA on big dataset with automationFlow automation skills in standard cells development and integration to improve execution efficiency. Experience of using Python/TCL/PerlKnowledge of FE modeling/Verilog and/or VHDL, and experience with various EDA tools for characterization, synthesis, place-route, Verilog simulation, spice simulation, formal verification, DRC/LVS, RC extraction and/or library characterization. Proven understanding of device physics and process.Familiar with foundry ecosystem and benchmarking practice.