Senior Standard Cell Design Lead | Library & Timing Expert

Substrate; San Francisco (CA); On-site; USD 150,000 - 400,000; Full time

Job summary

A leading semiconductor technology company is seeking a Standard Cell Design Lead to develop and optimize standard cell libraries. You will lead efforts in cell characterization and library validation, working on innovative solutions within a dynamic team. This role is based in San Francisco and requires 10+ years of experience in standard cell design and deep technical expertise in digital design flows. Competitive salary offered.

Qualifications

• 10+ years experience in standard cell design, library development and characterization.
• Deep understanding of standard cell architecture, layout, and optimization strategies.
• Strong background in cell characterization and Liberty timing model generation.

Responsibilities

• Lead standard cell library development including logic gates, flip-flops, and complex cells.
• Optimize cell layouts for power, performance and area across Vth’s and drive strengths.
• Characterize cell library including timing, power, and noise analysis for library models.
• Collaborate with PDK and process teams to ensure cell performance meets targets.

Skills

Standard cell design

Library development

Cell characterization

Power analysis

Layout optimization

Education

Advanced degree in Electrical Engineering or related field

Tools

Cadence Virtuoso

Synopsys Custom Compiler

SPICE simulation

Job description

A leading semiconductor technology company is seeking a Standard Cell Design Lead to develop and optimize standard cell libraries. You will lead efforts in cell characterization and library validation, working on innovative solutions within a dynamic team. This role is based in San Francisco and requires 10+ years of experience in standard cell design and deep technical expertise in digital design flows. Competitive salary offered.