Senior Staff FPGA Clocking & PLL Design Engineer

Advanced Micro Devices, Inc.; San Jose (CA); Vor Ort; USD 180.000 - 240.000; Vollzeit

Zusammenfassung

AMD is seeking a Staff Design Engineer to lead PLL design and integration for FPGA products. You will work across process nodes, guiding analog/mixed-signal IPs and PLL topologies while collaborating with cross-functional teams to optimize performance and reliability.

You will contribute to post-silicon validation, system-level simulations, and lab bring-up, leveraging Vivado tools to validate clocking solutions in cutting-edge SoCs.

Qualifikationen

• Solid foundation in IC design and manufacturing including analog/digital IP integration (e.g., PLLs, LDOs, Phase Interpolators)
• Strong understanding of device physics, reliability, and silicon chip manufacturing
• Passion for adaptive computing architectures and post-silicon validation and characterization
• Collaborative, cross-team communication and strong analytical/problem-solving skills

Aufgaben

• Architect and integrate analog/mixed-signal PLL building blocks into FPGA products across cutting-edge process nodes
• Lead integration of PLL topologies (integer-N, fractional-N, ADPLL) to meet power, area, jitter, and frequency specifications
• Address challenges in advanced node technologies (self-heating, electromigration, VCO linearization, noise optimization) for jitter optimization
• Supervise and verify layouts produced by PD engineers for floorplanning, matching, and parasitic minimization
• Own PLL bring-up in the lab and perform performance characterization with state-of-the-art equipment
• Conduct system-level simulations and validation for PLL IP integration in FPGA environments using Vivado or similar tools/flows

Kenntnisse

PLL design

FPGA clocking

Analog/digital IP integration

IC design

Silicon validation

Ausbildung

MS in Electrical & Electronics Engineering

Bachelor's degree with relevant experience

Tools

Vivado

Jobbeschreibung

AMD is seeking a Staff Design Engineer to lead PLL design and integration for FPGA products. You will work across process nodes, guiding analog/mixed-signal IPs and PLL topologies while collaborating with cross-functional teams to optimize performance and reliability.

You will contribute to post-silicon validation, system-level simulations, and lab bring-up, leveraging Vivado tools to validate clocking solutions in cutting-edge SoCs.