Senior Clocking Engineer - Analog Mixed-Signal PLLs

Octopyd; Sunnyvale (CA); On-site; USD 180,000 - 270,000; Full time

Job summary

Avicena in Sunnyvale, CA is seeking a Senior/Principal Analog Mixed-Signal Design Engineer, Clocking to own clock generation and distribution across multiple high-speed lanes.

You will drive PLL/DLL integration, jitter budgets, phase alignment, and collaboration with system architects, layout, and verification through silicon bring-up. Prior leadership and strong analytical skills are essential.

Qualifications

• MS or BS with clocking design experience and 5+ years.
• Experience with PLL, DLL, phase interpolators or CDR.
• Experience with post-layout extraction and sign-off.
• Knowledge of jitter/phase-noise analysis tools.

Responsibilities

• Design and integrate clocking circuits: PLLs (licensed IP and custom blocks), clock receivers and buffers, phase interpolators or DLLs, duty-cycle correction and phase alignment.
• Design low-jitter clock distribution across many lanes.
• Analyze jitter and phase noise, and maintain the jitter budget with the clocking lead and system architect.
• Evaluate licensed PLL IP against requirements and support its integration.
• Analyze supply sensitivity and coupling, and work with layout on clock routing and shielding.
• Deliver behavioral models for system and verification use, and correlate them with transistor-level results.
• Support silicon bring-up and jitter measurement correlation.

Skills

Clocking circuit design

Jitter analysis

CMOS FinFET design

Post-layout signoff

Technical leadership

Education

MS in Electrical Engineering

BS with equivalent experience

Tools

Spectre RF (PSS/pnoise)

MATLAB

Python

Job description

Avicena in Sunnyvale, CA is seeking a Senior/Principal Analog Mixed-Signal Design Engineer, Clocking to own clock generation and distribution across multiple high-speed lanes.

You will drive PLL/DLL integration, jitter budgets, phase alignment, and collaboration with system architects, layout, and verification through silicon bring-up. Prior leadership and strong analytical skills are essential.