Senior Staff FPGA Clocking Architect—PLL/IP Expert

AMD; San Jose (CA); On-site; USD 150,000 - 220,000; Full time

Job summary

AMD in San Jose, CA seeks a Staff Design Engineer to lead PLL design, integration and verification for FPGA products. You will work with Analog/Digital IPs, LDOs, Phase Interpolators, and advanced node challenges to deliver robust clocking solutions across AMD's programmable logic portfolio.

Ideal candidates have strong IC design foundations, systems modeling, and Hands-on experience with Vivado and mixed-signal PLLs.

Qualifications

• Solid foundation in IC design and manufacturing.
• Experience with analog/digital IP integration (PLLs, LDOs, Phase Interpolators).
• Background in chip design, silicon processes and packaging technologies.
• Strong understanding of device physics and reliability in silicon manufacturing.

Responsibilities

• Architect and integrate analog/mixed-signal PLL blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) into FPGA products.
• Lead integration of PLL topologies (integer-N, fractional-N, ADPLL) for power, area, jitter, and frequency range.
• Address advanced node challenges such as self-heating, electromigration, VCO linearization and noise optimization.
• Supervise and verify PD layouts to ensure floor planning, matching, and parasitic minimization.
• Be responsible for PLL bring-up in the lab and perform performance characterization with modern lab equipment.
• Conduct system-level simulations and validation for PLL IP integration in FPGA environments using Vivado or similar tools/flows.

Skills

IC design

Analog IP integration

Digital IP integration

SystemVerilog modeling

Clock synthesis & recovery

Vivado

Device physics

Reliability considerations

Education

MS in electrical & electronics engineering

Bachelor's degree + experience

Tools

Vivado

Job description

AMD in San Jose, CA seeks a Staff Design Engineer to lead PLL design, integration and verification for FPGA products. You will work with Analog/Digital IPs, LDOs, Phase Interpolators, and advanced node challenges to deliver robust clocking solutions across AMD's programmable logic portfolio.

Ideal candidates have strong IC design foundations, systems modeling, and Hands-on experience with Vivado and mixed-signal PLLs.