Staff CPU RTL Engineer, Silicon

Google; Mountain View (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google is hiring in Mountain View, CA for a senior RTL design engineer focused on CPU subsystems and AI accelerators. You will define microarchitecture, implement front-end RTL, and optimize for performance, power, and area while collaborating with Software, Architect, and Verification teams.

We value experience with SystemVerilog, UPF/Lint, and a strong grasp of PPA trade‑offs. Individual pay includes bonus and equity, with a broad benefits package.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience in CPU or AI accelerator logic/RTL design, including microarchitecture definition and PPA optimizations.
• Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF).

Responsibilities

• Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing microarchitecture and RTL design for the next generation CPU.
• Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade‑off studies.
• Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality.
• Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
• Become familiar with modern techniques, interpret the techniques into design constructs, and languages to provide guidance to and participate in the performance evaluation effort.

Skills

RTL design

SystemVerilog

PPA optimization

microarchitecture

communication

Education

Bachelor's degree or equivalent

Master's or PhD preferred

Tools

Lint

UPF

ARM ISA

SOC design

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Portland, OR, USA; Mountain View, CA, USA.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in CPU or AI accelerator logic/RTL design, including microarchitecture definition and PPA optimizations.
• Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience leading front-end design for modern processor components or AI accelerators.
• Experience with ARM Instruction Set Architecture.
• Experience with SOC design, architect, and integration.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
• Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade‑off studies.
• Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality.
• Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
• Become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation effort.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .