Staff CPU RTL Engineer, Silicon

Google LLC; Austin, Portland (TX, OR); On-site; USD 192,000 - 278,000; Full time

Job summary

Google LLC in Austin, TX is seeking a senior hardware engineer to design CPU subsystems and front-end RTL for next-generation AI accelerators.

The role requires a strong background in microarchitecture, SystemVerilog, and collaboration with software and architecture teams; English proficiency and willingness to work across locations.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, CS, or related field, or equivalent experience.
• 8 years of CPU/AI accelerator RTL design experience, incl. microarchitecture and PPA optimizations.
• Experience with RTL (SystemVerilog) and design processes (Lint, UPF).

Responsibilities

• Develop CPU subsystem front-end designs focusing on microarchitecture and RTL for the next-generation CPU.
• Propose microarchitecture enhancements and collaborate with Software, Architect and Performance teams.
• Explain microarchitecture trade-offs and deliver designs meeting PPA goals with production quality.
• Work with Verification, Physical Design and Power teams to meet frequency, power and area targets.
• Learn modern techniques and translate them into design constructs to guide and participate in performance evaluation.

Skills

RTL design

SystemVerilog

microarchitecture

PPA optimization

CPU subsystems

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD preferred

Tools

ARM ISA

UPF

Job description

corporate_fare Google place Austin, TX, USA ; Portland, OR, USA ; +1 more

In most instances, this position requires in-person interviews as part of the hiring process. Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Portland, OR, USA; Mountain View, CA, USA.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in CPU or AI accelerator logic/RTL design, including microarchitecture definition and PPA optimizations.
• Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience leading front-end design for modern processor components or AI accelerators.
• Experience with ARM Instruction Set Architecture.
• Experience with SOC design, architect, and integration.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

• Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
• Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade-off studies.
• Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality.
• Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
• Become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation effort.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.