CPU Performance Architect

Google; Mountain View (CA); On-site; USD 163,000 - 237,000; Full time

Job summary

Google in Mountain View, CA is seeking a CPU Performance Architect to push boundaries in silicon design. You will lead deep-dive analyses, develop models, and collaborate with CPU architects to optimize performance and power across diverse workloads.

Qualifications include a Bachelor's in EE/CE/CS, 8 years in performance analysis, and proficiency with C/C++ and Python. This role offers impact on next-generation hardware and equity benefits.

Qualifications

• Bachelor's degree in EE/CE/CS or equivalent practical experience.
• 8 years of experience with performance analysis, microarchitectural bottleneck isolation, and workload characterization.
• Experience with C/C++ for architectural modeling and Python for data analysis and automation frameworks.

Responsibilities

• Lead deep-dive microarchitectural analysis on silicon to isolate and quantify pipeline stalls, memory hierarchy bottlenecks, and instruction-level inefficiencies to drive root-cause resolution.
• Design, build, and execute advanced power and performance experiments on physical silicon to rigorously correlate pre-silicon projections with post-silicon reality across general-purpose and AI/ML compute workloads.
• Develop and maintain early-stage power and performance models to evaluate complex architectural 'what-if' scenarios, driving hardware-software co-optimization.
• Partner closely with lead CPU architects and cross-functional teams to define dynamic, realistic power and performance goals for future Google silicon.

Skills

Performance analysis

Microarchitectural bottleneck

Workload characterization

C/C++

Python

Architectural modeling

Education

Bachelor's degree or equivalent

Job description

CPU Performance Architect

Google

Mountain View, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with performance analysis, microarchitectural bottleneck isolation, and workload characterization.
• Experience with C/C++ for architectural modeling and scripting languages (specifically Python) for data analysis and automation frameworks.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with the ARM instruction set architecture (ISA) and ecosystem.
• Experience characterizing and optimizing mobile or client platform power/performance and thermal management states (e.g., DVFS).
• Understanding of low-level system software components, including the Linux kernel, device drivers, power management frameworks, and runtimes.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits

Responsibilities

• Lead deep-dive microarchitectural analysis on silicon to isolate and quantify pipeline stalls, memory hierarchy bottlenecks, and instruction-level inefficiencies to drive root-cause resolution.
• Design, build, and execute advanced power and performance experiments on physical silicon to rigorously correlate pre-silicon projections with post-silicon reality across general-purpose and AI/ML compute workloads.
• Develop and maintain early-stage power and performance models to evaluate complex architectural "what-if" scenarios, driving hardware-software co-optimization.
• Partner closely with lead CPU architects and cross-functional teams to define dynamic, realistic power and performance goals for future Google silicon.

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