Senior Staff Applications Engineer - Physical Design & CTS

Synopsys Inc; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys Inc. seeks an experienced ASIC physical design expert to lead advanced node flows in Sunnyvale, CA. You will work directly with customers, debugging timing and routing challenges while developing AI-driven optimization and CTS methodologies.

You will collaborate with product teams to translate customer needs into tool improvements, train engineers on Fusion Compiler, ICC2, and PrimeTime, and travel up to 30% for on-site support.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent with 9+ years of hands-on ASIC physical design experience, or Master's with 7+ years.
• Deep expertise in RTL-to-GDSII flows with placement, optimization, clock tree synthesis, and routing.
• Hands-on proficiency with Synopsys backend tools including Fusion Compiler, ICC2, Design Compiler, and PrimeTime.
• Experience with timing closure techniques and multi-scenario optimization in complex SoC designs.

Responsibilities

• Support pre-sales and post-sales engagements with semiconductor customers, demonstrating Synopsys physical design tools including Fusion Compiler and ICC2 in live technical sessions
• Debug complex physical design issues across the RTL-to-GDSII flow, working directly with customer design teams to resolve placement, routing, timing closure, and congestion challenges at advanced nodes
• Develop and deliver technical methodologies for clock tree synthesis, AI-driven optimization, macro placement, and timing closure that customers can adopt in production flows
• Build proof-of-concept designs and benchmarks that show measurable PPA improvements using Synopsys tools compared to customer baseline flows
• Collaborate with product engineering teams to translate customer pain points into feature requests, tool enhancements, and methodology improvements
• Train customer engineers on advanced Synopsys tool capabilities, from multi-scenario optimization to noise-aware routing techniques
• Travel to customer sites to provide hands-on technical support during critical project phases, including tape-out preparation and bring-up

Skills

ASIC physical design

RTL-to-GDSII flows

Clock tree synthesis

Timing closure

Customer engagement

Technical training

Travel readiness

Education

Bachelor's degree in Electrical Engineering

Master's degree

Tools

Fusion Compiler

ICC2

Design Compiler

PrimeTime

Job description

Synopsys Inc. seeks an experienced ASIC physical design expert to lead advanced node flows in Sunnyvale, CA. You will work directly with customers, debugging timing and routing challenges while developing AI-driven optimization and CTS methodologies.

You will collaborate with product teams to translate customer needs into tool improvements, train engineers on Fusion Compiler, ICC2, and PrimeTime, and travel up to 30% for on-site support.