Senior STA Signoff Architect for Next-Gen GPU Timing

NVIDIA; United States; On-site; USD 196,000 - 311,000; Full time

Job summary

NVIDIA seeks an innovative Senior STA Signoff Methodology Engineer to drive sign-off strategies for GPUs, CPUs, LPUs and SoCs. This role optimizes performance, yield, and reliability through modeling, insightful analysis, and automation.

You'll collaborate with technology leads, physical-design and timing engineers to deploy sophisticated timing-signoff strategies. Strong FinFET/CMOS knowledge and industry tools are valued.

Qualifications

• MS in Electrical or Computer Engineering, or equivalent experience, with 8 years of ASIC design and timing.
• Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
• Proven foundation in the mathematics and physics underlying electrical design.
• Experience with low-power techniques, including multi-Vt design, clock gating, power gating, DVFS, and CDC.
• Understanding of signal and power integrity, crosstalk, electromigration, noise, OCV, timing margins, clock jitter, and IR drop.
• Understanding of standard-cell, memory, and I/O IP modeling and their use in ASIC flows.
• Hands-on experience with advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm, and beyond.
• Familiarity with industry-standard ASIC tools such as PrimeTime, ICC2, RedHawk, and Tempus.
• Strong communication skills and a collaborative working style.

Responsibilities

• Run large-scale SPICE simulations and STA experiments to model the impact of advanced technologies on chip timing.
• Develop STA and PNR flows and recommendations addressing aging, self-heating, thermal effects, IR drop, electro migration, and other advanced-node physical effects.
• Collaborate with technology leads, physical-design engineers, and timing engineers to define and deploy sophisticated timing-signoff strategies for extraordinary silicon performance.
• Develop tools and methodologies that improve design performance, predictability, and silicon reliability beyond the capabilities of standard EDA tools.
• Work across STA, constraints, and timing and power optimization.
• Perform extensive data analysis using Python, JMP, or similar tools to improve STA-to-silicon correlation.

Skills

ASIC design

Timing analysis

RC extraction

Device physics

Power integrity

Python

Education

MS in Electrical or Computer Engineering

Tools

PrimeTime

ICC2

RedHawk

Tempus

Job description

NVIDIA seeks an innovative Senior STA Signoff Methodology Engineer to drive sign-off strategies for GPUs, CPUs, LPUs and SoCs. This role optimizes performance, yield, and reliability through modeling, insightful analysis, and automation.

You'll collaborate with technology leads, physical-design and timing engineers to deploy sophisticated timing-signoff strategies. Strong FinFET/CMOS knowledge and industry tools are valued.