Senior STA Engineer — CPU Sign-Off & Margin Expert

MediaTek Research Lab Inc.; Austin (TX); On-site; USD 152,400 - 217,200; Full time

Benefits offered by this job

Performance bonus

Health insurance

401K and more

Job summary

MediaTek invites applications for a Senior STA Engineer to lead block‑level sign‑off for high‑performance CPU blocks. You will work with PD, RTL, and DFT teams to ensure clean sign‑off and robust timing closures while developing advanced margining techniques.

This role emphasizes collaboration across design disciplines and ongoing contribution to next‑gen margin methodologies. The position requires 5+ years in STA for high‑GHz CPUs, strong knowledge of OCV/AOCV/POCV, and proficiency with

Qualifications

• 5+ years of STA experience on high‑performance CPU designs (≥2 GHz).
• Expert‑level understanding of multi‑scenario STA, SDC constraints, and timing exceptions.
• Deep knowledge of OCV/AOCV/POCV margining and silicon correlation.
• Multi‑OPP closure experience across wide voltage‑frequency range.
• Familiarity with clock tree timing analysis and co‑optimization with physical design.
• Proficiency with Tcl, Python, or Perl scripting.
• Advanced‑node tape‑out experience (7nm or below).

Responsibilities

• Own block‑level STA sign‑off: constraint development, multi‑scenario regression, and timing closure.
• Generate and drive timing and power ECOs through to resolution.
• Partner with RTL and DFT teams to define accurate functional and test‑mode constraints.
• Develop and champion advanced margining methodologies calibrated to silicon.
• Analyze clock tree quality; guide physical implementation toward scalable convergence.
• Build custom sign‑off recipes for power recovery and timing closure in Tempus/PrimeTime.
• Deliver timing models and SDC/timing budgets for SoC integration.
• Participate in MediaTek's worldwide STA forum; help define next‑generation margin methodologies.

Skills

STA experience

Timing closure

OCV/AOCV/POCV margining

Clock tree analysis

Scripting (Tcl/Python/Perl)

Sign-off tools experience

Tools

Cadence Tempus

Synopsys PrimeTime

Job description

MediaTek invites applications for a Senior STA Engineer to lead block‑level sign‑off for high‑performance CPU blocks. You will work with PD, RTL, and DFT teams to ensure clean sign‑off and robust timing closures while developing advanced margining techniques.

This role emphasizes collaboration across design disciplines and ongoing contribution to next‑gen margin methodologies. The position requires 5+ years in STA for high‑GHz CPUs, strong knowledge of OCV/AOCV/POCV, and proficiency with