Staff Timing Engineer — GPU IP Timing & Signoff Expert

Samsung; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Samsung Austin Research and Development Center (SARC) seeks a Staff Timing (STA) Engineer to ensure timing integrity for next‑gen GPU IPs used in mobile and automotive segments.

The role combines hands-on timing at the top level with collaboration across RTL, physical design, and EDA partners to deliver reliable timing closure, power recovery, and signoff readiness in a fast-paced, global team.

Qualifications

• 6+ years experience with a Bachelor's in Computer Science/Engineering, or 4+ years with a Master's, or 2+ years with a Ph.D.
• Solid understanding of ASIC design flows and electrical fundamentals.
• Working knowledge of POCV, derating methodologies, and timing analysis.
• Strong hands-on experience with industry STA tools (e.g., PrimeTime, Tempus).
• Solid hands-on experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs.
• Working knowledge of formal equivalency checks, low-power checks, timing constraints, UPF.
• Strong scripting in Tcl, Perl, Shell, and/or Python.
• Strong analytical skills, attention to detail, and data-driven problem solving.
• Excellent communication and collaboration skills.

Responsibilities

• Perform hands-on timing analysis at top level and contribute to timing convergence and signoff readiness.
• Collaborate with RTL, physical design, SoC integration, and EDA partners to resolve timing issues.
• Apply timing budgeting, derating, and multi-voltage methodologies across advanced nodes.
• Identify tool gaps, influence flow improvements, and support model extraction and timing robustness.

Skills

Timing analysis

GPU/ASIC knowledge

Data-driven problem solving

Collaboration

Scripting (Python/Tcl)

Education

Bachelor's in CS/Engineering

Master's in CS/Engineering

PhD

Tools

PrimeTime

Tempus

CTS

UPF

Job description

Samsung Austin Research and Development Center (SARC) seeks a Staff Timing (STA) Engineer to ensure timing integrity for next‑gen GPU IPs used in mobile and automotive segments.

The role combines hands-on timing at the top level with collaboration across RTL, physical design, and EDA partners to deliver reliable timing closure, power recovery, and signoff readiness in a fast-paced, global team.