Staff STA CAD Engineer: Timing, Automation & Signoff

Samsung Electronics Perú; Austin (TX); On-site; USD 151,000 - 227,000; Full time

Benefits offered by this job

Medical

Dental

Vision

Life Insurance

401(k)

Onsite lunch

Employee purchase program

Tuition assistance

Paid time off

Student loans

Wellness incentives

Job summary

Samsung Austin Research and Development Center is seeking a Staff STA CAD Engineer to ensure timing integrity and signoff readiness for next‑generation GPU IPs used in premium devices. You will work with design teams and EDA partners to optimize timing analysis flows and automation.

In this mid‑level role, you will implement robust STA methodologies, apply AI techniques to improve efficiency, and contribute to cross‑functional timing closure across modes and power domains.

Qualifications

• 6+ years experience with a Bachelor’s in CS/Engineering, or 4+ with a Master, or 2+ with a PhD.
• Solid understanding of ASIC design flows and electrical fundamentals.
• Hands-on with LLE, POCV, derating methodologies, and timing analysis.
• Experience with industry STA tools including PrimeTime, StarRC, PrimeClosure, Tempus.
• CTS, multi-voltage and multi-clock designs experience.
• Knowledge of UPF, formal checks, and timing constraints.
• Scripting in Tcl, Python, Perl, and Shell.
• Strong analytical, communication, and collaboration skills.

Responsibilities

• Ensure timing integrity and signoff readiness for next‑gen GPU IPs.
• Collaborate with design and EDA partners to develop automation for timing analysis.
• Develop flows for timing closure across functional and test modes.
• Test and debug STA methodologies and sign-off flows; document results.
• Apply AI to improve engineering task efficiency and accuracy.

Skills

STA experience

ASIC flows

Scripting Tcl/Python

UPF knowledge

CTS/Clock flows

POCV/derating

Automation

Education

Bachelor’s in CS/Engineering

Master’s degree

PhD

Tools

PrimeTime

StarRC

PrimeClosure

Tempus

Job description

Samsung Austin Research and Development Center is seeking a Staff STA CAD Engineer to ensure timing integrity and signoff readiness for next‑generation GPU IPs used in premium devices. You will work with design teams and EDA partners to optimize timing analysis flows and automation.

In this mid‑level role, you will implement robust STA methodologies, apply AI techniques to improve efficiency, and contribute to cross‑functional timing closure across modes and power domains.